Fix some SliceSels not being constants (#3186) (#3218).

.gitignore

@@ -39,3 +39,4 @@ verilator-config-version.cmake
 **/__pycache__/*
 **/_build/*
 **/obj_dir/*
+/.vscode/

docs/CONTRIBUTORS

@@ -64,6 +64,7 @@ Marshal Qiao
 Martin Schmidt
 Matthew Ballance
 Michael Killough
+Michaël Lefebvre
 Mike Popoloski
 Miodrag Milanović
 Morten Borup Petersen

src/V3Const.cpp

@@ -3430,7 +3430,7 @@ private:
     virtual void visit(AstNode* nodep) override {
         // Default: Just iterate
         if (m_required) {
-            if (VN_IS(nodep, NodeDType) || VN_IS(nodep, Range)) {
+            if (VN_IS(nodep, NodeDType) || VN_IS(nodep, Range) || VN_IS(nodep, SliceSel)) {
                 // Ignore dtypes for parameter type pins
             } else {
                 nodep->v3error("Expecting expression to be constant, but can't convert a "

test_regress/t/t_const_slicesel.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+
+scenarios(linter => 1);
+
+lint(
+);
+
+ok(1);
+1;

test_regress/t/t_const_slicesel.v

@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Michael Lefebvre.
+
+
+module t(/*AUTOARG*/);
+
+localparam int unsigned A2 [1:0] = '{5,6};
+localparam int unsigned A3 [2:0] = '{4,5,6};
+
+// Matching sizes with slicesel are okay.
+localparam int unsigned B22 [1:0] = A2[1:0];
+localparam int unsigned B33 [2:0] = A3[2:0];
+
+// bug #3186
+localparam int unsigned B32_B [1:0] = A3[1:0];
+localparam int unsigned B32_T [1:0] = A3[2:1];
+
+endmodule

test_regress/t/t_const_slicesel_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1
+);
+
+ok(1);
+1;

test_regress/t/t_const_slicesel_bad.v

@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Michael Lefebvre.
+
+
+module t(/*AUTOARG*/);
+
+localparam int unsigned A3 [2:0] = '{4,5,6};
+
+// slicesel out of range should fail
+localparam int unsigned B32_T [1:0] = A3[3:1];
+
+endmodule