Fix parsing for sequence expressions (#6427)
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
This commit is contained in:
Bartłomiej Chmiel
GitHub
parent
f53ca6ceee
commit
9a6b24fca4
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@ -6311,7 +6311,9 @@ property_port_itemDirE:
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;
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property_declarationBody<nodep>: // IEEE: part of property_declaration
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assertion_variable_declarationList
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assertion_variable_declarationList property_spec
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{ $$ = nullptr; BBUNSUP($1->fileline(), "Unsupported: property variable declaration"); DEL($1); }
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| assertion_variable_declarationList property_spec ';'
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{ $$ = nullptr; BBUNSUP($1->fileline(), "Unsupported: property variable declaration"); DEL($1); }
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// // IEEE-2012: Incorrectly has yCOVER ySEQUENCE then property_spec here.
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// // Fixed in IEEE 1800-2017
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@ -6384,6 +6386,8 @@ property_spec<propSpecp>: // IEEE: property_spec
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{ $$ = new AstPropSpec{$1, $3, $8, $10}; }
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| '@' '(' senitem ')' pexpr
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{ $$ = new AstPropSpec{$1, $3, nullptr, $5}; }
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| '@' senitemVar pexpr
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{ $$ = new AstPropSpec{$1, $2, nullptr, $3}; }
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// // Disable applied after the event occurs,
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// // so no existing AST can represent this
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| yDISABLE yIFF '(' expr ')' '@' '(' senitemEdge ')' pexpr
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@ -6567,7 +6571,7 @@ sexpr<nodeExprp>: // ==IEEE: sequence_expr (The name sexpr is important as reg
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// // IEEE: "cycle_delay_range sequence_expr { cycle_delay_range sequence_expr }"
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// // IEEE: "sequence_expr cycle_delay_range sequence_expr { cycle_delay_range sequence_expr }"
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// // Both rules basically mean we can repeat sequences, so make it simpler:
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cycle_delay_range sexpr %prec yP_POUNDPOUND
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cycle_delay_range ~p~sexpr %prec yP_POUNDPOUND
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{ $$ = $2; BBUNSUP($2->fileline(), "Unsupported: ## (in sequence expression)"); }
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| ~p~sexpr cycle_delay_range sexpr %prec prPOUNDPOUND_MULTI
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{ $$ = $1; BBUNSUP($2->fileline(), "Unsupported: ## (in sequence expression)"); }
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@ -6589,7 +6593,8 @@ sexpr<nodeExprp>: // ==IEEE: sequence_expr (The name sexpr is important as reg
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// // '(' sequence_expr {',' sequence_match_item } ')' [ boolean_abbrev ]
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// // "'(' sexpr ')' boolean_abbrev" matches "[sexpr:'(' expr ')'] boolean_abbrev" so we can drop it
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| '(' ~p~sexpr ')' { $$ = $2; }
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//UNSUP '(' ~p~sexpr ',' sequence_match_itemList ')' { }
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| '(' ~p~sexpr ',' sequence_match_itemList ')'
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{ $$ = $2; BBUNSUP($3, "Unsupported sequence match items"); }
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//
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// // AND/OR are between pexprs OR sexprs
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| ~p~sexpr yAND ~p~sexpr
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@ -28,7 +28,7 @@ module t(/*AUTOARG*/
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc);
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$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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@ -43,12 +43,17 @@ module t(/*AUTOARG*/
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`checkd(test.count_hits_iff, 48);
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`checkd(test.count_hits_implies, 24);
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`checkd(test.count_hits_not, 47);
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`checkd(test.count_hits_event, 1);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @(negedge clk) begin
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if (cyc == 10) -> test.e;
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end
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endmodule
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module Test(input clk,
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@ -59,6 +64,8 @@ module Test(input clk,
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int count_hits_iff;
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int count_hits_implies;
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int count_hits_not;
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int count_hits_event;
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event e;
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default disable iff cyc < 5;
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@ -73,4 +80,6 @@ module Test(input clk,
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assert property ( @(negedge clk) not a )
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else count_hits_not = count_hits_not + 1;
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assert property ( @e not a )
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else count_hits_event = count_hits_event + 1;
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endmodule
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@ -0,0 +1,122 @@
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:46:35: Unsupported: ## () cycle delay range expression
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46 | assert property (@(posedge clk) ##2 val)
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| ^~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:46:39: Unsupported: ## (in sequence expression)
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46 | assert property (@(posedge clk) ##2 val)
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:49:35: Unsupported: ## () cycle delay range expression
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49 | assert property (@(posedge clk) ##1 1 |=> 0)
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:49:39: Unsupported: ## (in sequence expression)
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49 | assert property (@(posedge clk) ##1 1 |=> 0)
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| ^
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:52:35: Unsupported: ## () cycle delay range expression
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52 | assert property (@(posedge clk) ##1 1 |=> not (val))
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:52:39: Unsupported: ## (in sequence expression)
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52 | assert property (@(posedge clk) ##1 1 |=> not (val))
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| ^
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:55:35: Unsupported: ## () cycle delay range expression
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55 | assert property (@(posedge clk) ##1 val)
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:55:39: Unsupported: ## (in sequence expression)
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55 | assert property (@(posedge clk) ##1 val)
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:58:35: Unsupported: ## () cycle delay range expression
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58 | assert property (@(posedge clk) ##1 (val))
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:58:40: Unsupported: ## (in sequence expression)
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58 | assert property (@(posedge clk) ##1 (val))
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:61:36: Unsupported: ## () cycle delay range expression
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61 | assert property (@(posedge clk) (##1 (val)))
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:61:41: Unsupported: ## (in sequence expression)
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61 | assert property (@(posedge clk) (##1 (val)))
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:64:36: Unsupported: ## () cycle delay range expression
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64 | assert property (@(posedge clk) (##1 (val)))
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:64:41: Unsupported: ## (in sequence expression)
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64 | assert property (@(posedge clk) (##1 (val)))
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:67:40: Unsupported: ## () cycle delay range expression
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67 | assert property (@(posedge clk) not (##1 val))
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:67:44: Unsupported: ## (in sequence expression)
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67 | assert property (@(posedge clk) not (##1 val))
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:70:35: Unsupported: ## () cycle delay range expression
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70 | assert property (@(posedge clk) ##1 1 |=> 1)
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:70:39: Unsupported: ## (in sequence expression)
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70 | assert property (@(posedge clk) ##1 1 |=> 1)
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| ^
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:73:35: Unsupported: ## () cycle delay range expression
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73 | assert property (@(posedge clk) ##1 val |=> not val)
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:73:39: Unsupported: ## (in sequence expression)
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73 | assert property (@(posedge clk) ##1 val |=> not val)
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:76:35: Unsupported: ## () cycle delay range expression
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76 | assert property (@(posedge clk) ##1 (val) |=> not (val))
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:76:40: Unsupported: ## (in sequence expression)
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76 | assert property (@(posedge clk) ##1 (val) |=> not (val))
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:82:57: Unsupported: ## () cycle delay range expression
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82 | assert property (@(posedge clk) disable iff (cyc < 3) ##1 1 |=> cyc > 3)
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:82:61: Unsupported: ## (in sequence expression)
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82 | assert property (@(posedge clk) disable iff (cyc < 3) ##1 1 |=> cyc > 3)
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| ^
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:85:36: Unsupported: ## () cycle delay range expression
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85 | assert property (@(posedge clk) (##1 val) |=> (##1 val))
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:85:40: Unsupported: ## (in sequence expression)
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85 | assert property (@(posedge clk) (##1 val) |=> (##1 val))
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:85:50: Unsupported: ## () cycle delay range expression
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85 | assert property (@(posedge clk) (##1 val) |=> (##1 val))
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:85:54: Unsupported: ## (in sequence expression)
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85 | assert property (@(posedge clk) (##1 val) |=> (##1 val))
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:103:14: Unsupported sequence match items
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103 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b];
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| ^
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:103:29: Unsupported: ## range cycle delay range expression
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103 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b];
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:103:39: Unsupported: ## (in sequence expression)
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103 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b];
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| ^
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:102:13: Unsupported: property variable declaration
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102 | integer l_b;
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:120:16: Unsupported sequence match items
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120 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5;
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| ^
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:120:35: Unsupported: ## () cycle delay range expression
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120 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5;
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:120:51: Unsupported: [-> boolean abbrev expression
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120 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5;
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:120:54: Unsupported: boolean abbrev (in sequence expression)
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120 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5;
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| ^
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:120:37: Unsupported: ## (in sequence expression)
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120 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5;
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| ^
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:118:14: Unsupported: property variable declaration
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118 | realtime l_t;
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| ^~~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:124:31: Unsupported: ## () cycle delay range expression
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124 | assert property (@clk not a ##1 b);
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| ^~
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%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:124:33: Unsupported: ## (in sequence expression)
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124 | assert property (@clk not a ##1 b);
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| ^
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%Error: Exiting due to
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.lint(expect_filename=test.golden_filename,
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verilator_flags2=['--assert', '--timing', '--error-limit 1000'],
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fails=True)
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test.passes()
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@ -0,0 +1,125 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 1;
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bit val = 0;
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Test test ( /*AUTOINST*/
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// Inputs
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.clk(clk),
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.val(val),
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.cyc(cyc)
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);
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Ieee ieee();
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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val = ~val;
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`ifdef TEST_VERBOSE
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$display("cyc=%0d, val=%0d", cyc, val);
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`endif
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module Test (
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input clk,
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input bit val,
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input integer cyc
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);
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assert property (@(posedge clk) ##2 val)
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) ##1 1 |=> 0)
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) ##1 1 |=> not (val))
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) ##1 val)
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) ##1 (val))
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) (##1 (val)))
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) (##1 (val)))
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) not (##1 val))
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) ##1 1 |=> 1)
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) ##1 val |=> not val)
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) ##1 (val) |=> not (val))
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) ((val) |=> not (val)))
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) disable iff (cyc < 3) ##1 1 |=> cyc > 3)
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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assert property (@(posedge clk) (##1 val) |=> (##1 val))
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else $display("[%0t] assertion triggered, fileline:%d", $time, `__LINE__);
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endmodule
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// Test parsing only
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module Ieee;
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// IEEE 1800-2023 16.6
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bit a;
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integer b;
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byte q[$];
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logic clk;
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property p1;
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$rose(a) |-> q[0];
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endproperty
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property p2;
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integer l_b;
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($rose(a), l_b = b) |-> ##[3:10] q[l_b];
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endproperty
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bit [2:0] count = 0;
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realtime t;
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always @(posedge clk) begin
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if (count == 0) t = $realtime;
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count++;
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end
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property p3;
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@(posedge clk)
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count == 7 |-> $realtime - t < 50.5;
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endproperty
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property p4;
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realtime l_t;
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@(posedge clk)
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(count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5;
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endproperty
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// IEEE 1800-2023 16.12.3
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assert property (@clk not a ##1 b);
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endmodule
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@ -1,11 +1,10 @@
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%Error-UNSUPPORTED: t/t_property_var_unsup.v:18:13: Unsupported sequence match items
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18 | (valid, prevcyc = cyc) |=> (cyc == prevcyc + 1);
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| ^
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_property_var_unsup.v:17:11: Unsupported: property variable declaration
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17 | int prevcyc;
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| ^~~~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error: t/t_property_var_unsup.v:18:7: syntax error, unexpected '(', expecting endproperty
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18 | (valid, prevcyc = cyc) |=> (cyc == prevcyc + 1);
|
||||
| ^
|
||||
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
|
||||
%Error-UNSUPPORTED: t/t_property_var_unsup.v:24:31: Unsupported: property variable default value
|
||||
24 | property with_def(int nine = 9);
|
||||
| ^
|
||||
|
|
|
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Reference in New Issue