Commentary: Changes update

Changes

@@ -11,17 +11,27 @@ contributors that suggested or implemented a given issue are shown in []. Thanks
 Verilator 5.049 devel
 ==========================
 
+* Support `s_eventually` (#7291) (#7508). [Bartłomiej Chmiel, Antmicro Ltd.]
 * Support `always` / `always[m:n]` / `s_always[m:n]` property operators (#7482). [Yilou Wang]
+* Support rand_mode() on static rand class members (#7484) (#7510). [Yilou Wang]
 * Support `randomize() with (identifier_list) {constraint_block}` (#7486) (#7507). [Yilou Wang]
+* Support functions on RHS of force (#7491). [Artur Bieniek, Antmicro Ltd.]
 * Support `obj.randomize(null)` (#7487) (#7509). [Yilou Wang]
+* Support randsequence production function ports (#7522). [Yilou Wang]
+* Support followed-by operators `#-#` and `#=#` in properties (#7523). [Yilou Wang]
+* Improve `--coverage-fsm` (#7490). [Yogish Sekhar]
 * Fix inlining static initializer in V3Gate (#5381) (#7503). [Andrew Nolte] [Geza Lore, Testorrent USA, Inc.]
 * Fix generic interface port forwarded to a nested instance (#7454) (#7457). [Yilou Wang]
 * Fix internal error on multi-cycle SVA under default clocking (#7472) (#7506). [Yilou Wang]
 * Fix internal error instead of missing prototype error (#7485). [Alex Solomatnikov]
 * Fix mailbox#(packed_struct) type mismatch with parameterized class (#7494) (#7495). [Nikolai Kumar]
 * Fix std::randomize internal error on static member of different class (#7498) (#7499). [Alex Solomatnikov]
+* Fix assert under assert error (#7500) (#7513). [Nikolai Kumar]
+* Fix std::unique_ptr with incomplete type for clang (#7501) (#7526).
 * Fix virtual interface method call inlining and IMPURE suppression (#7505). [Nikolay Puzanov]
 * Fix expression coverage in loops (#7511). [Todd Strader]
+* Fix $bits on local struct with chained-interface (#7515) (#7517).
+* Fix array indexing side effects in compound assignments (#7519). [Kamil Danecki, Antmicro Ltd.]
 
 
 Verilator 5.048 2026-04-26

docs/internals.rst

@@ -1768,6 +1768,12 @@ LCOV_EXCL_BR_LINE``.
 The assertions ``UASSERT`` and similar are automatically excluded from
 coverage, and as such should not require exclusion meta comments.
 
+As getting to complete code coverage typically takes many passes,
+developers should please iterate coverage improvements using a personal
+machine, or a personal branch on GitHub with personal action runners,
+rather than the Verilator GitHub runners, to avoid lots of mail to watchers
+and CI queue blockage.
+
 
 Fuzzing
 -------
@@ -2262,9 +2268,6 @@ IEEE 1800-2023 31 Timing checks
 IEEE 1800-2023 32 SDF annotation
    No longer relevant with static timing analysis tools.
 
-IEEE 1800-2023 33 Config
-   Little industry use.
-
 
 Test Driver
 ===========

test_regress/t/t_cover_fsm_case_next_ok_multi.out

@@ -20,7 +20,7 @@
           } state_t;
         
           logic [1:0] aux;
-          state_t state_q /*verilator fsm_reset_arc*/;
+          state_t state_q  /*verilator fsm_reset_arc*/;
           state_t state_d;
         
           initial aux = 2'b00;
@@ -44,7 +44,8 @@
           always_ff @(posedge clk) begin
             if (rst) begin
               state_q <= S0;
-            end else begin
+            end
+            else begin
               state_q <= state_d;
             end
           end
@@ -61,7 +62,7 @@
             S2 = 2'b10
           } state_t;
         
-          state_t state_q /*verilator fsm_reset_arc*/;
+          state_t state_q  /*verilator fsm_reset_arc*/;
           state_t state_d;
           state_t other_d;
         
@@ -84,7 +85,8 @@
           always_ff @(posedge clk) begin
             if (rst) begin
               state_q <= S0;
-            end else begin
+            end
+            else begin
               state_q <= state_d;
             end
           end
@@ -98,9 +100,15 @@
           integer cyc;
         
           fsm_case_next_other_assign_ok case_next_other_assign_ok_u (
-              .clk(clk), .rst(rst), .start(start));
+              .clk(clk),
+              .rst(rst),
+              .start(start)
+          );
           fsm_case_next_other_lhs_ok case_next_other_lhs_ok_u (
-              .clk(clk), .rst(rst), .start(start));
+              .clk(clk),
+              .rst(rst),
+              .start(start)
+          );
         
           initial begin
             rst = 1'b1;

test_regress/t/t_cover_fsm_case_next_ok_multi.v

@@ -19,7 +19,7 @@ module fsm_case_next_other_assign_ok (
   } state_t;
 
   logic [1:0] aux;
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
 
   initial aux = 2'b00;
@@ -36,7 +36,8 @@ module fsm_case_next_other_assign_ok (
   always_ff @(posedge clk) begin
     if (rst) begin
       state_q <= S0;
-    end else begin
+    end
+    else begin
       state_q <= state_d;
     end
   end
@@ -53,7 +54,7 @@ module fsm_case_next_other_lhs_ok (
     S2 = 2'b10
   } state_t;
 
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
   state_t other_d;
 
@@ -69,7 +70,8 @@ module fsm_case_next_other_lhs_ok (
   always_ff @(posedge clk) begin
     if (rst) begin
       state_q <= S0;
-    end else begin
+    end
+    else begin
       state_q <= state_d;
     end
   end
@@ -83,9 +85,15 @@ module t (
   integer cyc;
 
   fsm_case_next_other_assign_ok case_next_other_assign_ok_u (
-      .clk(clk), .rst(rst), .start(start));
+      .clk(clk),
+      .rst(rst),
+      .start(start)
+  );
   fsm_case_next_other_lhs_ok case_next_other_lhs_ok_u (
-      .clk(clk), .rst(rst), .start(start));
+      .clk(clk),
+      .rst(rst),
+      .start(start)
+  );
 
   initial begin
     rst = 1'b1;

test_regress/t/t_cover_fsm_case_next_ok_multi_incl.out

@@ -20,7 +20,7 @@
           } state_t;
         
           logic [1:0] aux;
-          state_t state_q /*verilator fsm_reset_arc*/;
+          state_t state_q  /*verilator fsm_reset_arc*/;
           state_t state_d;
         
           initial aux = 2'b00;
@@ -44,7 +44,8 @@
           always_ff @(posedge clk) begin
             if (rst) begin
               state_q <= S0;
-            end else begin
+            end
+            else begin
               state_q <= state_d;
             end
           end
@@ -61,7 +62,7 @@
             S2 = 2'b10
           } state_t;
         
-          state_t state_q /*verilator fsm_reset_arc*/;
+          state_t state_q  /*verilator fsm_reset_arc*/;
           state_t state_d;
           state_t other_d;
         
@@ -84,7 +85,8 @@
           always_ff @(posedge clk) begin
             if (rst) begin
               state_q <= S0;
-            end else begin
+            end
+            else begin
               state_q <= state_d;
             end
           end
@@ -98,9 +100,15 @@
           integer cyc;
         
           fsm_case_next_other_assign_ok case_next_other_assign_ok_u (
-              .clk(clk), .rst(rst), .start(start));
+              .clk(clk),
+              .rst(rst),
+              .start(start)
+          );
           fsm_case_next_other_lhs_ok case_next_other_lhs_ok_u (
-              .clk(clk), .rst(rst), .start(start));
+              .clk(clk),
+              .rst(rst),
+              .start(start)
+          );
         
           initial begin
             rst = 1'b1;

test_regress/t/t_cover_fsm_if_unknown_enum_multi_bad.v

@@ -16,7 +16,7 @@ module unknown_then (
   } state_t;
 
   logic sel;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
 
   always_comb begin
@@ -43,7 +43,7 @@ module unknown_else (
   } state_t;
 
   logic sel;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
 
   always_comb begin
@@ -69,7 +69,7 @@ module unknown_direct (
     S1 = 2'd1
   } state_t;
 
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
 
   always_comb begin
@@ -97,7 +97,7 @@ module unknown_reset (
 
   logic rst;
   integer cyc;
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
 
   initial begin
@@ -125,7 +125,8 @@ module unknown_reset (
       /* verilator lint_off ENUMVALUE */
       state_q <= 2'd3;
       /* verilator lint_on ENUMVALUE */
-    end else begin
+    end
+    else begin
       state_q <= state_d;
     end
   end
@@ -133,8 +134,8 @@ endmodule
 
 module t;
   logic clk;
-  unknown_then unknown_then_u(.clk(clk));
-  unknown_else unknown_else_u(.clk(clk));
-  unknown_direct unknown_direct_u(.clk(clk));
-  unknown_reset unknown_reset_u(.clk(clk));
+  unknown_then unknown_then_u (.clk(clk));
+  unknown_else unknown_else_u (.clk(clk));
+  unknown_direct unknown_direct_u (.clk(clk));
+  unknown_reset unknown_reset_u (.clk(clk));
 endmodule

test_regress/t/t_cover_fsm_plain_always_ignore_multi.v

@@ -18,7 +18,7 @@ module ignore_sel_expr (
     S2 = 2'd2
   } state_t;
 
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
 
   // Plain always with a non-VarRef selector should be ignored silently.
@@ -49,7 +49,7 @@ module ignore_other_selector (
     S2 = 2'd2
   } state_t;
 
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
 
   // Plain always with an unrelated selector should also be ignored silently.
@@ -75,8 +75,8 @@ module t (
   logic other;
   integer cyc;
 
-  ignore_sel_expr ignore_sel_expr_u(.*);
-  ignore_other_selector ignore_other_selector_u(.*);
+  ignore_sel_expr ignore_sel_expr_u (.*);
+  ignore_other_selector ignore_other_selector_u (.*);
 
   initial begin
     rst = 1'b1;

test_regress/t/t_cover_fsm_plain_always_warn_multi_bad.v

@@ -15,7 +15,7 @@ module warn_edge (
     S2 = 2'd2
   } state_t;
 
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
 
   // Plain edge-sensitive next-state logic should warn even when the selector
@@ -46,7 +46,7 @@ module warn_case_next (
     S2 = 2'd2
   } state_t;
 
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
 
   // Plain always also warns for the near-supported case(state_d) style.
@@ -76,7 +76,7 @@ module warn_default_incl (
     S2 = 2'd2
   } state_t;
 
-  state_t state_q /*verilator fsm_reset_arc*/ /*verilator fsm_arc_include_cond*/;
+  state_t state_q  /*verilator fsm_reset_arc*/  /*verilator fsm_arc_include_cond*/;
   state_t state_d;
 
   // default becomes supported only because include_cond is set, but the block
@@ -100,7 +100,7 @@ module t;
   logic rst;
   logic start;
 
-  warn_edge warn_edge_u(.*);
-  warn_case_next warn_case_next_u(.*);
-  warn_default_incl warn_default_incl_u(.*);
+  warn_edge warn_edge_u (.*);
+  warn_case_next warn_case_next_u (.*);
+  warn_default_incl warn_default_incl_u (.*);
 endmodule

test_regress/t/t_cover_fsm_plain_always_zerohit_multi.v

@@ -18,7 +18,7 @@ module near_canonical_state_d_case (
     S2 = 2'd2
   } state_t;
 
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
 
   // Unsupported for the plain-always warning scan: case(state_d) is only
@@ -49,7 +49,7 @@ module selector_matches_noassign (
   } state_t;
 
   logic other;
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
 
   // The selector matches the FSM state, but the case body never assigns
@@ -76,8 +76,8 @@ module t (
   logic start;
   integer cyc;
 
-  near_canonical_state_d_case near_canonical_state_d_case_u(.*);
-  selector_matches_noassign selector_matches_noassign_u(.*);
+  near_canonical_state_d_case near_canonical_state_d_case_u (.*);
+  selector_matches_noassign selector_matches_noassign_u (.*);
 
   initial begin
     rst = 1'b1;

test_regress/t/t_cover_fsm_policy_accept_multi.out

@@ -25,7 +25,8 @@
           always_ff @(posedge clk) begin
             if (rst) begin
               state <= S0;
-            end else begin
+            end
+            else begin
 %000003       case (state)
         // [FSM coverage]
 %000001        // [fsm_arc t.style_u.state::ANY->S0[reset]] [reset arc, excluded from %]
@@ -58,7 +59,7 @@
             S2 = 2'd2
           } state_t;
         
-          state_t state_q /*verilator fsm_arc_include_cond*/;
+          state_t state_q  /*verilator fsm_arc_include_cond*/;
           state_t state_d;
         
           always_comb begin
@@ -92,7 +93,8 @@
           always_ff @(posedge clk) begin
             if (rst) begin
               state <= 2'd0;
-            end else begin
+            end
+            else begin
 %000002       case (state)
         // [FSM coverage]
 %000001        // [fsm_arc t.forced_u.state::ANY->S0[reset]] [reset arc, excluded from %]
@@ -117,9 +119,20 @@
           logic rst;
           logic start;
         
-          fsm_style_incl style_u (.clk(clk), .rst(rst), .start(start));
-          fsm_default_incl_ok default_incl_u (.clk(clk), .rst(rst), .start(start));
-          fsm_forced_ok forced_u (.clk(clk), .rst(rst));
+          fsm_style_incl style_u (
+              .clk(clk),
+              .rst(rst),
+              .start(start)
+          );
+          fsm_default_incl_ok default_incl_u (
+              .clk(clk),
+              .rst(rst),
+              .start(start)
+          );
+          fsm_forced_ok forced_u (
+              .clk(clk),
+              .rst(rst)
+          );
         
           initial begin
             cyc = 0;

test_regress/t/t_cover_fsm_policy_accept_multi.v

@@ -24,7 +24,8 @@ module fsm_style_incl (
   always_ff @(posedge clk) begin
     if (rst) begin
       state <= S0;
-    end else begin
+    end
+    else begin
       case (state)
         S0:
         if (start) state <= S1;
@@ -47,7 +48,7 @@ module fsm_default_incl_ok (
     S2 = 2'd2
   } state_t;
 
-  state_t state_q /*verilator fsm_arc_include_cond*/;
+  state_t state_q  /*verilator fsm_arc_include_cond*/;
   state_t state_d;
 
   always_comb begin
@@ -73,7 +74,8 @@ module fsm_forced_ok (
   always_ff @(posedge clk) begin
     if (rst) begin
       state <= 2'd0;
-    end else begin
+    end
+    else begin
       case (state)
         2'd0: state <= 2'd1;
         2'd1: state <= 2'd2;
@@ -90,9 +92,20 @@ module t (
   logic rst;
   logic start;
 
-  fsm_style_incl style_u (.clk(clk), .rst(rst), .start(start));
-  fsm_default_incl_ok default_incl_u (.clk(clk), .rst(rst), .start(start));
-  fsm_forced_ok forced_u (.clk(clk), .rst(rst));
+  fsm_style_incl style_u (
+      .clk(clk),
+      .rst(rst),
+      .start(start)
+  );
+  fsm_default_incl_ok default_incl_u (
+      .clk(clk),
+      .rst(rst),
+      .start(start)
+  );
+  fsm_forced_ok forced_u (
+      .clk(clk),
+      .rst(rst)
+  );
 
   initial begin
     cyc = 0;

test_regress/t/t_cover_fsm_transition_shapes_multi.v

@@ -19,7 +19,7 @@ module fsm_caseitem_varrhs_bad (
 
   logic start;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
   state_t other_d;
 
@@ -59,7 +59,7 @@ module fsm_caseitem_then_nonconst_bad (
 
   logic sel;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
   state_t other_d;
 
@@ -100,7 +100,7 @@ module fsm_caseitem_else_nonconst_bad (
 
   logic sel;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
   state_t other_d;
 
@@ -143,7 +143,7 @@ module fsm_oneblock_then_bad (
   logic rst;
   logic sel;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
 
   initial begin
@@ -186,7 +186,7 @@ module fsm_oneblock_else_bad (
   logic rst;
   logic sel;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
 
   initial begin
@@ -229,7 +229,7 @@ module fsm_combo_sel_expr_bad (
   logic rst;
   logic start;
   integer cyc;
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
 
   initial begin
@@ -256,7 +256,8 @@ module fsm_combo_sel_expr_bad (
   always_ff @(posedge clk) begin
     if (rst) begin
       state_q <= S0;
-    end else begin
+    end
+    else begin
       state_q <= state_d;
     end
   end
@@ -265,11 +266,15 @@ endmodule
 module fsm_normalized_if_noelse_bad (
     input logic clk
 );
-  typedef enum logic [1:0] { S0 = 2'd0, S1 = 2'd1, S2 = 2'd2 } state_t;
+  typedef enum logic [1:0] {
+    S0 = 2'd0,
+    S1 = 2'd1,
+    S2 = 2'd2
+  } state_t;
   logic rst;
   logic start;
   integer cyc;
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
 
   initial begin
@@ -286,7 +291,9 @@ module fsm_normalized_if_noelse_bad (
   always_comb begin
     state_d = state_q;
     case (state_q)
-      S0: if (start) ; else state_d = S1;
+      S0:
+      if (start);
+      else state_d = S1;
       default: state_d = S0;
     endcase
   end
@@ -299,10 +306,14 @@ endmodule
 module fsm_normalized_if_then_nonconst_bad (
     input logic clk
 );
-  typedef enum logic [1:0] { S0 = 2'd0, S1 = 2'd1, S2 = 2'd2 } state_t;
+  typedef enum logic [1:0] {
+    S0 = 2'd0,
+    S1 = 2'd1,
+    S2 = 2'd2
+  } state_t;
   logic sel;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
   state_t tmp_a;
   state_t tmp_b;
@@ -337,10 +348,14 @@ endmodule
 module fsm_normalized_if_else_nonconst_bad (
     input logic clk
 );
-  typedef enum logic [1:0] { S0 = 2'd0, S1 = 2'd1, S2 = 2'd2 } state_t;
+  typedef enum logic [1:0] {
+    S0 = 2'd0,
+    S1 = 2'd1,
+    S2 = 2'd2
+  } state_t;
   logic sel;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
   state_t tmp_a;
   state_t tmp_b;
@@ -375,10 +390,14 @@ endmodule
 module fsm_normalized_if_temp_mismatch_bad (
     input logic clk
 );
-  typedef enum logic [1:0] { S0 = 2'd0, S1 = 2'd1, S2 = 2'd2 } state_t;
+  typedef enum logic [1:0] {
+    S0 = 2'd0,
+    S1 = 2'd1,
+    S2 = 2'd2
+  } state_t;
   logic sel;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
   state_t tmp_a;
   state_t tmp_b;
@@ -411,10 +430,14 @@ endmodule
 module fsm_normalized_if_then_state_else_other_bad (
     input logic clk
 );
-  typedef enum logic [1:0] { S0 = 2'd0, S1 = 2'd1, S2 = 2'd2 } state_t;
+  typedef enum logic [1:0] {
+    S0 = 2'd0,
+    S1 = 2'd1,
+    S2 = 2'd2
+  } state_t;
   logic sel;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
   state_t tmp_a;
 
@@ -446,11 +469,15 @@ endmodule
 module fsm_normalized_if_same_temp_nofollow_bad (
     input logic clk
 );
-  typedef enum logic [1:0] { S0 = 2'd0, S1 = 2'd1, S2 = 2'd2 } state_t;
+  typedef enum logic [1:0] {
+    S0 = 2'd0,
+    S1 = 2'd1,
+    S2 = 2'd2
+  } state_t;
   logic sel;
   logic aux;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
   state_t tmp_a;
 
@@ -470,7 +497,8 @@ module fsm_normalized_if_same_temp_nofollow_bad (
         if (sel) begin
           tmp_a = S1;
           aux = 1'b1;
-        end else begin
+        end
+        else begin
           tmp_a = S2;
           aux = 1'b0;
         end
@@ -486,11 +514,15 @@ endmodule
 module fsm_normalized_if_follow_nonvar_bad (
     input logic clk
 );
-  typedef enum logic [1:0] { S0 = 2'd0, S1 = 2'd1, S2 = 2'd2 } state_t;
+  typedef enum logic [1:0] {
+    S0 = 2'd0,
+    S1 = 2'd1,
+    S2 = 2'd2
+  } state_t;
   logic sel;
   logic aux;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
   state_t tmp_a;
 
@@ -510,7 +542,8 @@ module fsm_normalized_if_follow_nonvar_bad (
         if (sel) begin
           tmp_a = S1;
           aux = 1'b1;
-        end else begin
+        end
+        else begin
           tmp_a = S2;
           aux = 1'b0;
         end
@@ -528,11 +561,15 @@ endmodule
 module fsm_normalized_if_follow_wrongfrom_bad (
     input logic clk
 );
-  typedef enum logic [1:0] { S0 = 2'd0, S1 = 2'd1, S2 = 2'd2 } state_t;
+  typedef enum logic [1:0] {
+    S0 = 2'd0,
+    S1 = 2'd1,
+    S2 = 2'd2
+  } state_t;
   logic sel;
   logic aux;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
   state_t tmp_a;
   state_t other_d;
@@ -553,7 +590,8 @@ module fsm_normalized_if_follow_wrongfrom_bad (
         if (sel) begin
           tmp_a = S1;
           aux = 1'b1;
-        end else begin
+        end
+        else begin
           tmp_a = S2;
           aux = 1'b0;
         end
@@ -571,11 +609,15 @@ endmodule
 module fsm_normalized_if_follow_wronglhs_bad (
     input logic clk
 );
-  typedef enum logic [1:0] { S0 = 2'd0, S1 = 2'd1, S2 = 2'd2 } state_t;
+  typedef enum logic [1:0] {
+    S0 = 2'd0,
+    S1 = 2'd1,
+    S2 = 2'd2
+  } state_t;
   logic sel;
   logic aux;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
   state_t tmp_a;
   state_t other_d;
@@ -596,7 +638,8 @@ module fsm_normalized_if_follow_wronglhs_bad (
         if (sel) begin
           tmp_a = S1;
           aux = 1'b1;
-        end else begin
+        end
+        else begin
           tmp_a = S2;
           aux = 1'b0;
         end
@@ -614,11 +657,15 @@ endmodule
 module fsm_case_next_wrongrhs_bad (
     input logic clk
 );
-  typedef enum logic [1:0] { S0 = 2'd0, S1 = 2'd1, S2 = 2'd2 } state_t;
+  typedef enum logic [1:0] {
+    S0 = 2'd0,
+    S1 = 2'd1,
+    S2 = 2'd2
+  } state_t;
   logic rst;
   logic start;
   integer cyc;
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
   state_t other_d;
 
@@ -672,7 +719,8 @@ module fsm_forced_wide_bad (
   always_ff @(posedge clk) begin
     if (rst) begin
       state <= 31'd0;
-    end else begin
+    end
+    else begin
       case (state)
         31'd0: state <= 31'd1;
         31'd1: state <= 31'd2;
@@ -696,7 +744,7 @@ module fsm_reset_commit_mismatch_bad (
   logic rst;
   logic start;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t other_q;
   state_t state_d;
 
@@ -745,7 +793,7 @@ module fsm_reset_then_bad (
   logic rst;
   logic sel;
   integer cyc;
-  state_t state_q /*verilator fsm_state*/;
+  state_t state_q  /*verilator fsm_state*/;
   state_t state_d;
 
   initial begin

test_regress/t/t_cover_fsm_two_proc_multi.out

@@ -15,12 +15,12 @@
         );
           typedef enum logic [1:0] {
             S_IDLE = 2'd0,
-            S_RUN  = 2'd1,
+            S_RUN = 2'd1,
             S_DONE = 2'd2,
-            S_ERR  = 2'd3
+            S_ERR = 2'd3
           } state_t;
         
-%000002   state_t state_q /*verilator fsm_reset_arc*/;
+%000002   state_t state_q  /*verilator fsm_reset_arc*/;
 %000002   state_t state_d;
         
  000010   always_comb begin
@@ -145,7 +145,7 @@
             S1 = 1'b1
           } state_t;
         
-%000001   state_t state_incl_q /*verilator fsm_reset_arc*/;
+%000001   state_t state_incl_q  /*verilator fsm_reset_arc*/;
 %000001   state_t state_incl_d;
 %000001   state_t state_excl_q;
 %000001   state_t state_excl_d;
@@ -421,17 +421,56 @@
 %000001   logic bit_done;
 %000001   logic sel;
         
-          fsm_basic basic_u (.clk(clk), .rst(rst), .start(start));
-          fsm_three_block three_block_u (.clk(clk), .rst(rst), .start(start));
-          fsm_mealy mealy_u (.clk(clk), .rst(rst), .start(start), .bit_done(bit_done));
-          fsm_reset_policy reset_u (.clk(clk), .rst(rst));
+          fsm_basic basic_u (
+              .clk(clk),
+              .rst(rst),
+              .start(start)
+          );
+          fsm_three_block three_block_u (
+              .clk(clk),
+              .rst(rst),
+              .start(start)
+          );
+          fsm_mealy mealy_u (
+              .clk(clk),
+              .rst(rst),
+              .start(start),
+              .bit_done(bit_done)
+          );
+          fsm_reset_policy reset_u (
+              .clk(clk),
+              .rst(rst)
+          );
           fsm_nextstate_sel_off nextstate_sel_off_u (.clk(clk));
-          fsm_nextstate_sel_ok nextstate_sel_ok_u (.clk(clk), .rst(rst), .start(start));
-          fsm_ternary ternary_u (.clk(clk), .rst(rst), .sel(sel));
-          fsm_plain_always plain_always_u (.clk(clk), .rst(rst), .go(start));
-          fsm_plain_always_list plain_always_list_u (.clk(clk), .rst(rst), .go(start));
-          fsm_caseassigns_off caseassigns_off_u (.clk(clk), .rst(rst), .go(start));
-          fsm_seqmix_off seqmix_off_u (.clk(clk), .rst(rst));
+          fsm_nextstate_sel_ok nextstate_sel_ok_u (
+              .clk(clk),
+              .rst(rst),
+              .start(start)
+          );
+          fsm_ternary ternary_u (
+              .clk(clk),
+              .rst(rst),
+              .sel(sel)
+          );
+          fsm_plain_always plain_always_u (
+              .clk(clk),
+              .rst(rst),
+              .go(start)
+          );
+          fsm_plain_always_list plain_always_list_u (
+              .clk(clk),
+              .rst(rst),
+              .go(start)
+          );
+          fsm_caseassigns_off caseassigns_off_u (
+              .clk(clk),
+              .rst(rst),
+              .go(start)
+          );
+          fsm_seqmix_off seqmix_off_u (
+              .clk(clk),
+              .rst(rst)
+          );
         
 %000001   initial begin
 %000001     cyc = 0;

test_regress/t/t_cover_fsm_two_proc_multi.v

@@ -14,12 +14,12 @@ module fsm_basic (
 );
   typedef enum logic [1:0] {
     S_IDLE = 2'd0,
-    S_RUN  = 2'd1,
+    S_RUN = 2'd1,
     S_DONE = 2'd2,
-    S_ERR  = 2'd3
+    S_ERR = 2'd3
   } state_t;
 
-  state_t state_q /*verilator fsm_reset_arc*/;
+  state_t state_q  /*verilator fsm_reset_arc*/;
   state_t state_d;
 
   always_comb begin
@@ -124,7 +124,7 @@ module fsm_reset_policy (
     S1 = 1'b1
   } state_t;
 
-  state_t state_incl_q /*verilator fsm_reset_arc*/;
+  state_t state_incl_q  /*verilator fsm_reset_arc*/;
   state_t state_incl_d;
   state_t state_excl_q;
   state_t state_excl_d;
@@ -364,17 +364,56 @@ module t (
   logic bit_done;
   logic sel;
 
-  fsm_basic basic_u (.clk(clk), .rst(rst), .start(start));
-  fsm_three_block three_block_u (.clk(clk), .rst(rst), .start(start));
-  fsm_mealy mealy_u (.clk(clk), .rst(rst), .start(start), .bit_done(bit_done));
-  fsm_reset_policy reset_u (.clk(clk), .rst(rst));
+  fsm_basic basic_u (
+      .clk(clk),
+      .rst(rst),
+      .start(start)
+  );
+  fsm_three_block three_block_u (
+      .clk(clk),
+      .rst(rst),
+      .start(start)
+  );
+  fsm_mealy mealy_u (
+      .clk(clk),
+      .rst(rst),
+      .start(start),
+      .bit_done(bit_done)
+  );
+  fsm_reset_policy reset_u (
+      .clk(clk),
+      .rst(rst)
+  );
   fsm_nextstate_sel_off nextstate_sel_off_u (.clk(clk));
-  fsm_nextstate_sel_ok nextstate_sel_ok_u (.clk(clk), .rst(rst), .start(start));
-  fsm_ternary ternary_u (.clk(clk), .rst(rst), .sel(sel));
-  fsm_plain_always plain_always_u (.clk(clk), .rst(rst), .go(start));
-  fsm_plain_always_list plain_always_list_u (.clk(clk), .rst(rst), .go(start));
-  fsm_caseassigns_off caseassigns_off_u (.clk(clk), .rst(rst), .go(start));
-  fsm_seqmix_off seqmix_off_u (.clk(clk), .rst(rst));
+  fsm_nextstate_sel_ok nextstate_sel_ok_u (
+      .clk(clk),
+      .rst(rst),
+      .start(start)
+  );
+  fsm_ternary ternary_u (
+      .clk(clk),
+      .rst(rst),
+      .sel(sel)
+  );
+  fsm_plain_always plain_always_u (
+      .clk(clk),
+      .rst(rst),
+      .go(start)
+  );
+  fsm_plain_always_list plain_always_list_u (
+      .clk(clk),
+      .rst(rst),
+      .go(start)
+  );
+  fsm_caseassigns_off caseassigns_off_u (
+      .clk(clk),
+      .rst(rst),
+      .go(start)
+  );
+  fsm_seqmix_off seqmix_off_u (
+      .clk(clk),
+      .rst(rst)
+  );
 
   initial begin
     cyc = 0;

test_regress/t/t_fsmmulti_combo_multi_warn_bad.out

@@ -1,15 +1,15 @@
-%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:34:21: FSM coverage: multiple supported transition candidates found in the same combinational always block. Only the first candidate will be instrumented.
-   34 |       B0: state_b_d = B1;
+%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:36:21: FSM coverage: multiple supported transition candidates found in the same combinational always block. Only the first candidate will be instrumented.
+   36 |       B0: state_b_d = B1;
       |                     ^
-                   t/t_fsmmulti_combo_multi_warn_bad.v:30:21: ... Location of first supported candidate for 't.same_u.state_a_q'
-   30 |       A0: state_a_d = A1;
+                   t/t_fsmmulti_combo_multi_warn_bad.v:32:21: ... Location of first supported candidate for 't.same_u.state_a_q'
+   32 |       A0: state_a_d = A1;
       |                     ^
                    ... For warning description see https://verilator.org/warn/FSMMULTI?v=latest
                    ... Use "/* verilator lint_off FSMMULTI */" and lint_on around source to disable this message.
-%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:70:19: FSM coverage: multiple supported transition candidates found for the same FSM in combinational always blocks. Only the first candidate will be instrumented.
-   70 |       S0: state_d = S1;
+%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:73:19: FSM coverage: multiple supported transition candidates found for the same FSM in combinational always blocks. Only the first candidate will be instrumented.
+   73 |       S0: state_d = S1;
       |                   ^
-                   t/t_fsmmulti_combo_multi_warn_bad.v:62:19: ... Location of first supported candidate for 't.split_u.state_q'
-   62 |       S0: state_d = S1;
+                   t/t_fsmmulti_combo_multi_warn_bad.v:65:19: ... Location of first supported candidate for 't.split_u.state_q'
+   65 |       S0: state_d = S1;
       |                   ^
 %Error: Exiting due to

test_regress/t/t_fsmmulti_combo_multi_warn_bad.v

@@ -11,11 +11,13 @@ module same_always_warn (
     input logic clk
 );
   typedef enum logic [1:0] {
-    A0, A1
+    A0,
+    A1
   } a_state_t;
 
   typedef enum logic [1:0] {
-    B0, B1
+    B0,
+    B1
   } b_state_t;
 
   a_state_t state_a_q;
@@ -50,7 +52,8 @@ module split_always_warn (
 );
   /* verilator lint_off MULTIDRIVEN */
   typedef enum logic [1:0] {
-    S0, S1
+    S0,
+    S1
   } state_t;
 
   state_t state_q;

test_regress/t/t_iface_chained_consumer_struct.v

@@ -10,20 +10,30 @@
 // passes $bits(struct) to a width-parameterized child.  All widths
 // must use the override value, not the template default.
 
-interface inner_if #(parameter int N = 1) ();
+interface inner_if #(
+    parameter int N = 1
+) ();
   typedef logic [$clog2(N)-1:0] id_t;
 endinterface
 
-interface mid_if #(parameter int N = 1) ();
-  inner_if #(.N(N)) inner();
+interface mid_if #(
+    parameter int N = 1
+) ();
+  inner_if #(.N(N)) inner ();
   typedef inner.id_t id_t;
 endinterface
 
-module sink #(parameter int W = 1) (input logic [W-1:0] dat_i);
+module sink #(
+    parameter int W = 1
+) (
+    input logic [W-1:0] dat_i
+);
 endmodule
 
-module dut #(parameter int N = 1) ();
-  mid_if #(.N(N)) m();
+module dut #(
+    parameter int N = 1
+) ();
+  mid_if #(.N(N)) m ();
   typedef m.id_t id_t;
   typedef struct packed {
     id_t id;
@@ -31,12 +41,12 @@ module dut #(parameter int N = 1) ();
   } pkt_t;
   pkt_t pkt_var;
   localparam int W = $bits(pkt_t);
-  sink #(.W(W)) s(.dat_i(pkt_var));
+  sink #(.W(W)) s (.dat_i(pkt_var));
 endmodule
 
 module t;
   // N=8 gives id_t = 3 bits, so pkt_t = 3 + 8 = 11 bits.
-  dut #(.N(8)) u();
+  dut #(.N(8)) u ();
 
   initial begin
     if (u.W !== 11) begin

test_regress/t/t_randomize_inside_cond.v

@@ -24,11 +24,11 @@ module t;
       assert((std::randomize(x) with {x inside {40, 50}; }) == 1)
       fail_count++;
 
-    if(pass_count != 1) begin
+    if (pass_count != 1) begin
       $display("FAIL: pass_count=%0d expected 1", pass_count);
       $stop;
     end
-    if(fail_count != 1) begin
+    if (fail_count != 1) begin
       $display("FAIL: fail_count=%0d expected 1", fail_count);
       $stop;
     end