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Support 'bit' keyword

This commit is contained in:
Wilson Snyder 2009-10-31 15:12:28 -04:00
parent 18bebaf5c3
commit 9a133ced2d
3 changed files with 20 additions and 8 deletions
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2
bin/verilator
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@ -1179,7 +1179,7 @@ including function call-like preprocessor defines.
Verilator supports ==? and !=? operators, $bits, $countones, $error, Verilator supports ==? and !=? operators, $bits, $countones, $error,
$fatal, $info, $isunknown, $onehot, $onehot0, $warning, always_comb, $fatal, $info, $isunknown, $onehot, $onehot0, $warning, always_comb,
always_ff, always_latch, do-while, final, logic, priority case/if, and always_ff, always_latch, bit, do-while, final, logic, priority case/if, and
unique case/if. unique case/if.
It also supports .name and .* interconnection. It also supports .name and .* interconnection.

2
src/verilog.l
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@ -360,6 +360,7 @@ escid \\[^ \t\f\r\n]+
"always_comb" { FL; return yALWAYS; } "always_comb" { FL; return yALWAYS; }
"always_ff" { FL; return yALWAYS; } "always_ff" { FL; return yALWAYS; }
"always_latch" { FL; return yALWAYS; } "always_latch" { FL; return yALWAYS; }
"bit" { FL; return yBIT; }
"clocking" { FL; return yCLOCKING; } "clocking" { FL; return yCLOCKING; }
"do" { FL; return yDO; } "do" { FL; return yDO; }
"endclocking" { FL; return yENDCLOCKING; } "endclocking" { FL; return yENDCLOCKING; }
@ -380,7 +381,6 @@ escid \\[^ \t\f\r\n]+
"bind" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "bind" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"bins" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "bins" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"binsof" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "binsof" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"bit" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"break" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "break" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"byte" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "byte" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"chandle" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "chandle" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }

24
src/verilog.y
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@ -206,6 +206,7 @@ class AstSenTree;
%token<fl> yASSIGN "assign" %token<fl> yASSIGN "assign"
%token<fl> yAUTOMATIC "automatic" %token<fl> yAUTOMATIC "automatic"
%token<fl> yBEGIN "begin" %token<fl> yBEGIN "begin"
%token<fl> yBIT "bit"
%token<fl> yBUF "buf" %token<fl> yBUF "buf"
%token<fl> yBUFIF0 "bufif0" %token<fl> yBUFIF0 "bufif0"
%token<fl> yBUFIF1 "bufif1" %token<fl> yBUFIF1 "bufif1"
@ -792,6 +793,21 @@ tf_port_declaration<nodep>: // ==IEEE: tf_port_declaration
//UNSUP port_directionReset yVAR implicit_type { VARTYPE($3); } list_of_tf_variable_identifiers ';' { $$ = $5; } //UNSUP port_directionReset yVAR implicit_type { VARTYPE($3); } list_of_tf_variable_identifiers ';' { $$ = $5; }
; ;
integer_atom_type<rangep>: // ==IEEE: integer_atom_type
//UNSUP yBYTE { UNSUP }
//UNSUP ySHORTINT { UNSUP }
//UNSUP yINT { UNSUP }
//UNSUP yLONGINT { UNSUP }
yINTEGER { VARDECL(INTEGER); $$ = new AstRange($1,31,0); $$->isSigned(true); }
//UNSUP yTIME { UNSUP }
;
integer_vector_type: // ==IEEE: integer_atom_type
yBIT { VARDECL(REG); }
| yLOGIC { VARDECL(REG); }
| yREG { VARDECL(REG); }
;
signingE: // IEEE: signing - plus empty signingE: // IEEE: signing - plus empty
/*empty*/ { } /*empty*/ { }
| signing { } | signing { }
@ -818,12 +834,8 @@ data_type<rangep>: // ==IEEE: data_type
; ;
data_typeNoRef<rangep>: // ==IEEE: data_type, excluding class_type etc references data_typeNoRef<rangep>: // ==IEEE: data_type, excluding class_type etc references
yINTEGER { VARDECL(INTEGER); $$ = new AstRange($1,31,0); $$->isSigned(true); } integer_vector_type signingE rangeListE { $$ = $3; }
| yREG signingE rangeListE { VARDECL(REG); $$ = $3; } | integer_atom_type signingE { $$ = $1; }
| yLOGIC signingE rangeListE { VARDECL(REG); $$ = $3; }
//UNSUP: above instead of integer_type
//
//UNSUP integer_type signingE regArRangeE { UNSUP }
//UNSUP non_integer_type { UNSUP } //UNSUP non_integer_type { UNSUP }
//UNSUP ySTRUCT packedSigningE '{' struct_union_memberList '}' packed_dimensionE { UNSUP } //UNSUP ySTRUCT packedSigningE '{' struct_union_memberList '}' packed_dimensionE { UNSUP }
//UNSUP yUNION taggedE packedSigningE '{' struct_union_memberList '}' packed_dimensionE { UNSUP } //UNSUP yUNION taggedE packedSigningE '{' struct_union_memberList '}' packed_dimensionE { UNSUP }