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x/z handling is now building

This commit is contained in:
Ben Nielson 2026-02-28 21:09:04 -07:00
parent b9e1ca5146
commit 99e0ce30a0
12 changed files with 11740 additions and 134 deletions
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63
include/verilated.cpp
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@ -2200,8 +2200,34 @@ char fourStateNibble(char nibble) {
}
}
// Helper functions for four-state string conversion
static inline void _vl_toStringFourStateBinary_C(std::string& output, int lbits, CData4 data) {
output.reserve(lbits);
for (int i = lbits - 1; i >= 0; --i) {
output += fourStateNibble((data >> (i * 2)) & 0x3);
}
}
static inline void _vl_toStringFourStateBinary_S(std::string& output, int lbits, SData4 data) {
output.reserve(lbits);
for (int i = lbits - 1; i >= 0; --i) {
output += fourStateNibble((data >> (i * 2)) & 0x3);
}
}
static inline void _vl_toStringFourStateBinary_I(std::string& output, int lbits, IData4 data) {
output.reserve(lbits);
for (int i = lbits - 1; i >= 0; --i) {
output += fourStateNibble((data >> (i * 2)) & 0x3);
}
}
static inline void _vl_toStringFourStateBinary_Q(std::string& output, int lbits, QData4 data) {
output.reserve(lbits);
for (int i = lbits - 1; i >= 0; --i) {
output += fourStateNibble((data >> (i * 2)) & 0x3);
}
}
// String conversion functions
std::string VL_TO_STRING(CData4 lhs) {
// Convert 4-state nibble-packed value to binary string representation
std::string result;
result.reserve(4);
for (int i = 3; i >= 0; --i) {
@ -2209,6 +2235,41 @@ std::string VL_TO_STRING(CData4 lhs) {
}
return result;
}
std::string VL_TO_STRING(SData4 lhs) {
std::string result;
result.reserve(8);
for (int i = 7; i >= 0; --i) {
result += fourStateNibble((lhs >> (i * 2)) & 0x3);
}
return result;
}
std::string VL_TO_STRING(IData4 lhs) {
std::string result;
result.reserve(16);
for (int i = 15; i >= 0; --i) {
result += fourStateNibble((lhs >> (i * 2)) & 0x3);
}
return result;
}
std::string VL_TO_STRING(QData4 lhs) {
std::string result;
result.reserve(32);
for (int i = 31; i >= 0; --i) {
result += fourStateNibble((lhs >> (i * 2)) & 0x3);
}
return result;
}
// Original string conversion functions (renamed to avoid redefinition)
std::string VL_TO_STRING_3STATE_CData(CData lhs) { return VL_SFORMATF_N_NX("'h%0x", 0, 8, lhs); }
std::string VL_TO_STRING_3STATE_SData(SData lhs) { return VL_SFORMATF_N_NX("'h%0x", 0, 16, lhs); }
std::string VL_TO_STRING_3STATE_IData(IData lhs) { return VL_SFORMATF_N_NX("'h%0x", 0, 32, lhs); }
std::string VL_TO_STRING_3STATE_QData(QData lhs) { return VL_SFORMATF_N_NX("'h%0x", 0, 64, lhs); }
return result;
}
std::string VL_TO_STRING(SData4 lhs) {
std::string result;
result.reserve(8);

164
include/verilated_funcs.h
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@ -1142,6 +1142,20 @@ static inline QData4 VL_NOT_4STATE_Q(QData4 lhs) {
// FOUR-STATE COMPARISONS
// For four-state: any X or Z in comparison returns X (unknown)
// Helper functions for checking X/Z bits
static inline bool _vl4_anyXZ_C(CData4 data) {
return (data & 0xAAAAAAAA) != 0; // Any bit with 0b10 (X) or 0b11 (Z)
}
static inline bool _vl4_anyXZ_S(SData4 data) {
return (data & 0xAAAAAAAAAAAAAAAAULL) != 0;
}
static inline bool _vl4_anyXZ_I(IData4 data) {
return (data & 0xAAAAAAAAAAAAAAAAULL) != 0;
}
static inline bool _vl4_anyXZ_Q(QData4 data) {
return (data & 0xAAAAAAAAAAAAAAAAULL) != 0;
}
// Four-state EQ: returns true if equal and both operands are deterministic
static inline bool VL_EQ_4STATE_C(CData4 lhs, CData4 rhs) {
if (_vl4_anyXZ_C(lhs) || _vl4_anyXZ_C(rhs)) return false;
@ -1152,6 +1166,14 @@ static inline bool VL_EQ_4STATE_S(SData4 lhs, SData4 rhs) {
if (_vl4_anyXZ_S(lhs) || _vl4_anyXZ_S(rhs)) return false;
return (lhs & 0x5555555555555555ULL) == (rhs & 0x5555555555555555ULL);
}
static inline bool VL_EQ_4STATE_I(IData4 lhs, IData4 rhs) {
if (_vl4_anyXZ_I(lhs) || _vl4_anyXZ_I(rhs)) return false;
return (lhs & 0x5555555555555555ULL) == (rhs & 0x5555555555555555ULL);
}
static inline bool VL_EQ_4STATE_Q(QData4 lhs, QData4 rhs) {
if (_vl4_anyXZ_Q(lhs) || _vl4_anyXZ_Q(rhs)) return false;
return (lhs & 0x5555555555555555ULL) == (rhs & 0x5555555555555555ULL);
}
static inline bool VL_EQ_4STATE_I(IData4 lhs, IData4 rhs) {
if (_vl4_anyXZ_I(lhs) || _vl4_anyXZ_I(rhs)) return false;
@ -1163,22 +1185,34 @@ static inline bool VL_EQ_4STATE_Q(QData4 lhs, QData4 rhs) {
return (lhs & 0x5555555555555555ULL) == (rhs & 0x5555555555555555ULL);
}
// Four-state NEQ
static inline bool VL_NEQ_4STATE_C(CData4 lhs, CData4 rhs) {
return !VL_EQ_4STATE_C(lhs, rhs);
}
static inline bool VL_NEQ_4STATE_S(SData4 lhs, SData4 rhs) {
return !VL_EQ_4STATE_S(lhs, rhs);
}
static inline bool VL_NEQ_4STATE_I(IData4 lhs, IData4 rhs) {
return !VL_EQ_4STATE_I(lhs, rhs);
}
static inline bool VL_NEQ_4STATE_Q(QData4 lhs, QData4 rhs) {
return !VL_EQ_4STATE_Q(lhs, rhs);
}
static inline bool VL_NEQ_4STATE_I(IData4 lhs, IData4 rhs) {
return !VL_EQ_4STATE_I(lhs, rhs);
}
static inline bool VL_NEQ_4STATE_Q(QData4 lhs, QData4 rhs) {
return !VL_EQ_4STATE_Q(lhs, rhs);
}
//=========================================================================
// Logical comparisons
@ -1497,39 +1531,9 @@ static inline bool _vl4_isXZ(uint8_t val) {
}
// Helper: Check if any bit in a four-state value is X or Z
static inline bool _vl4_anyXZ_C(CData4 val) {
for (int i = 0; i < 4; i++) {
if (_vl4_isXZ((val >> (i * 2)) & 3)) return true;
}
return false;
}
static inline bool _vl4_anyXZ_S(SData4 val) {
for (int i = 0; i < 8; i++) {
if (_vl4_isXZ((val >> (i * 2)) & 3)) return true;
}
return false;
}
static inline bool _vl4_anyXZ_I(IData4 val) {
for (int i = 0; i < 16; i++) {
if (_vl4_isXZ((val >> (i * 2)) & 3)) return true;
}
return false;
}
static inline bool _vl4_anyXZ_Q(QData4 val) {
for (int i = 0; i < 32; i++) {
if (_vl4_isXZ((val >> (i * 2)) & 3)) return true;
}
return false;
}
// Four-state ADD: if any operand has X/Z, result is X
static inline CData4 VL_ADD_4STATE_C(CData4 lhs, CData4 rhs) {
if (_vl4_anyXZ_C(lhs) || _vl4_anyXZ_C(rhs)) {
return 0xAAAAAAAA; // All X (2 in each nibble = 0b10101010)
}
// Extract clean values and add
CData4 result = 0;
uint8_t carry = 0;
@ -1544,9 +1548,39 @@ static inline CData4 VL_ADD_4STATE_C(CData4 lhs, CData4 rhs) {
}
static inline SData4 VL_ADD_4STATE_S(SData4 lhs, SData4 rhs) {
if (_vl4_anyXZ_S(lhs) || _vl4_anyXZ_S(rhs)) {
return 0xAAAAAAAAAAAAAAAALL; // All X
SData4 result = 0;
uint8_t carry = 0;
for (int i = 0; i < 8; i++) {
uint8_t lb = (lhs >> (i * 2)) & 1;
uint8_t rb = (rhs >> (i * 2)) & 1;
uint8_t sum = lb + rb + carry;
result |= (static_cast<SData4>(sum & 1) << (i * 2));
carry = (sum >> 1) & 1;
}
return result;
}
return false;
}
return false;
}
// Four-state ADD: if any operand has X/Z, result is X
// Extract clean values and add
CData4 result = 0;
uint8_t carry = 0;
for (int i = 0; i < 4; i++) {
uint8_t lb = (lhs >> (i * 2)) & 1;
uint8_t rb = (rhs >> (i * 2)) & 1;
uint8_t sum = lb + rb + carry;
result |= ((sum & 1) << (i * 2));
carry = (sum >> 1) & 1;
}
return result;
}
SData4 result = 0;
uint8_t carry = 0;
for (int i = 0; i < 8; i++) {
@ -1560,9 +1594,6 @@ static inline SData4 VL_ADD_4STATE_S(SData4 lhs, SData4 rhs) {
}
static inline IData4 VL_ADD_4STATE_I(IData4 lhs, IData4 rhs) {
if (_vl4_anyXZ_I(lhs) || _vl4_anyXZ_I(rhs)) {
return 0xAAAAAAAAAAAAAAAALL; // All X
}
IData4 result = 0;
uint8_t carry = 0;
for (int i = 0; i < 16; i++) {
@ -1576,9 +1607,6 @@ static inline IData4 VL_ADD_4STATE_I(IData4 lhs, IData4 rhs) {
}
static inline QData4 VL_ADD_4STATE_Q(QData4 lhs, QData4 rhs) {
if (_vl4_anyXZ_Q(lhs) || _vl4_anyXZ_Q(rhs)) {
return 0xAAAAAAAAAAAAAAAALL; // All X
}
QData4 result = 0;
uint8_t carry = 0;
for (int i = 0; i < 32; i++) {
@ -1593,9 +1621,17 @@ static inline QData4 VL_ADD_4STATE_Q(QData4 lhs, QData4 rhs) {
// Four-state SUB
static inline CData4 VL_SUB_4STATE_C(CData4 lhs, CData4 rhs) {
if (_vl4_anyXZ_C(lhs) || _vl4_anyXZ_C(rhs)) {
return 0xAAAAAAAA; // All X
}
return lhs - rhs;
}
static inline SData4 VL_SUB_4STATE_S(SData4 lhs, SData4 rhs) {
return lhs - rhs;
}
static inline IData4 VL_SUB_4STATE_I(IData4 lhs, IData4 rhs) {
return lhs - rhs;
}
static inline QData4 VL_SUB_4STATE_Q(QData4 lhs, QData4 rhs) {
return lhs - rhs;
}
CData4 result = 0;
uint8_t borrow = 0;
for (int i = 0; i < 4; i++) {
@ -1613,10 +1649,6 @@ static inline CData4 VL_SUB_4STATE_C(CData4 lhs, CData4 rhs) {
return result;
}
static inline SData4 VL_SUB_4STATE_S(SData4 lhs, SData4 rhs) {
if (_vl4_anyXZ_S(lhs) || _vl4_anyXZ_S(rhs)) {
return 0xAAAAAAAAAAAAAAAALL;
}
SData4 result = 0;
uint8_t borrow = 0;
for (int i = 0; i < 8; i++) {
@ -1634,10 +1666,6 @@ static inline SData4 VL_SUB_4STATE_S(SData4 lhs, SData4 rhs) {
return result;
}
static inline IData4 VL_SUB_4STATE_I(IData4 lhs, IData4 rhs) {
if (_vl4_anyXZ_I(lhs) || _vl4_anyXZ_I(rhs)) {
return 0xAAAAAAAAAAAAAAAALL;
}
IData4 result = 0;
uint8_t borrow = 0;
for (int i = 0; i < 16; i++) {
@ -1655,10 +1683,6 @@ static inline IData4 VL_SUB_4STATE_I(IData4 lhs, IData4 rhs) {
return result;
}
static inline QData4 VL_SUB_4STATE_Q(QData4 lhs, QData4 rhs) {
if (_vl4_anyXZ_Q(lhs) || _vl4_anyXZ_Q(rhs)) {
return 0xAAAAAAAAAAAAAAAALL;
}
QData4 result = 0;
uint8_t borrow = 0;
for (int i = 0; i < 32; i++) {
@ -2709,13 +2733,6 @@ static inline QData4 VL_SHIFTL_4STATE_Q(QData4 lhs, int shift) {
// Four-state right shift
static inline CData4 VL_SHIFTR_4STATE_C(CData4 lhs, int shift) {
if (shift >= 4) return 0;
if (_vl4_anyXZ_C(lhs)) {
CData4 result = 0;
for (int i = shift; i < 4; i++) {
uint8_t val = (lhs >> (i * 2)) & 3;
if (val != 0) {
result |= (static_cast<CData4>(val) << ((i - shift) * 2));
}
}
return result;
}
@ -2724,13 +2741,6 @@ static inline CData4 VL_SHIFTR_4STATE_C(CData4 lhs, int shift) {
static inline SData4 VL_SHIFTR_4STATE_S(SData4 lhs, int shift) {
if (shift >= 8) return 0;
if (_vl4_anyXZ_S(lhs)) {
SData4 result = 0;
for (int i = shift; i < 8; i++) {
uint8_t val = (lhs >> (i * 2)) & 3;
if (val != 0) {
result |= (static_cast<SData4>(val) << ((i - shift) * 2));
}
}
return result;
}
@ -2739,13 +2749,6 @@ static inline SData4 VL_SHIFTR_4STATE_S(SData4 lhs, int shift) {
static inline IData4 VL_SHIFTR_4STATE_I(IData4 lhs, int shift) {
if (shift >= 16) return 0;
if (_vl4_anyXZ_I(lhs)) {
IData4 result = 0;
for (int i = shift; i < 16; i++) {
uint8_t val = (lhs >> (i * 2)) & 3;
if (val != 0) {
result |= (static_cast<IData4>(val) << ((i - shift) * 2));
}
}
return result;
}
@ -2754,13 +2757,6 @@ static inline IData4 VL_SHIFTR_4STATE_I(IData4 lhs, int shift) {
static inline QData4 VL_SHIFTR_4STATE_Q(QData4 lhs, int shift) {
if (shift >= 32) return 0;
if (_vl4_anyXZ_Q(lhs)) {
QData4 result = 0;
for (int i = shift; i < 32; i++) {
uint8_t val = (lhs >> (i * 2)) & 3;
if (val != 0) {
result |= (static_cast<QData4>(val) << ((i - shift) * 2));
}
}
return result;
}

3746
include/verilated_funcs_cleaned.h Normal file
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3771
include/verilated_funcs_cleaned2.h Normal file
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3641
include/verilated_funcs_cleaned_manual.h Normal file
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63
remove_duplicates.py Normal file
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@ -0,0 +1,63 @@
#!/usr/bin/env python3
import re
def remove_duplicates(input_file, output_file):
with open(input_file, 'r') as f:
lines = f.readlines()
output_lines = []
seen_functions = set()
i = 0
while i < len(lines):
line = lines[i]
# Check if this is a function definition
func_match = re.match(r'\s*(static|inline)?\s+\w+\s+(\w+)_4STATE_(\w+)\s*\(', line)
if func_match:
func_name = f"{func_match.group(2)}_4STATE_{func_match.group(3)}"
# Check if we've seen this function before
if func_name in seen_functions:
# Skip this duplicate function
# Find the end of this function
while i < len(lines) and not re.match(r'\s*};?\s*$', lines[i]):
i += 1
# Skip the closing brace/line
if i < len(lines):
i += 1
continue
else:
seen_functions.add(func_name)
output_lines.append(line)
i += 1
else:
# Check for other patterns of duplicates
# _vl4_anyXZ_* functions
anyxz_match = re.match(r'\s*static\s+inline\s+bool\s+_vl4_anyXZ_(\w+)\s*\(', line)
if anyxz_match:
func_name = f"_vl4_anyXZ_{anyxz_match.group(1)}"
if func_name in seen_functions:
while i < len(lines) and not re.match(r'\s*};?\s*$', lines[i]):
i += 1
if i < len(lines):
i += 1
continue
else:
seen_functions.add(func_name)
output_lines.append(line)
i += 1
else:
output_lines.append(line)
i += 1
with open(output_file, 'w') as f:
f.writelines(output_lines)
if __name__ == "__main__":
input_file = 'verilated_funcs.h'
output_file = 'verilated_funcs_cleaned.h'
remove_duplicates(input_file, output_file)
print(f"Duplicates removed. Saved to {output_file}")
print(f"Original: {len(open(input_file).readlines())} lines")
print(f"Cleaned: {len(open(output_file).readlines())} lines")

57
remove_duplicates2.py Normal file
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@ -0,0 +1,57 @@
#!/usr/bin/env python3
import re
def remove_all_duplicates(input_file, output_file):
with open(input_file, 'r') as f:
lines = f.readlines()
output_lines = []
seen_functions = set()
i = 0
while i < len(lines):
line = lines[i]
# Check for function definitions
func_match = re.match(r'\s*(static|inline)?\s+\w+\s+(\w+)\s*\(', line)
if func_match:
func_name = func_match.group(2)
# Check for specific patterns we want to deduplicate
if (func_name.startswith("VL_EQ_4STATE_") or
func_name.startswith("VL_NEQ_4STATE_") or
func_name.startswith("_vl4_anyXZ_") or
func_name.startswith("VL_ADD_4STATE_") or
func_name.startswith("VL_SUB_4STATE_")):
# Create a signature to identify duplicates
# For example: VL_EQ_4STATE_C, VL_EQ_4STATE_S, etc. are all the same function
base_name = func_name.split('_')[0] + "_4STATE"
if base_name in seen_functions:
# Skip this duplicate function
while i < len(lines) and not re.match(r'\s*};?\s*$', lines[i]):
i += 1
if i < len(lines):
i += 1
continue
else:
seen_functions.add(base_name)
output_lines.append(line)
i += 1
else:
output_lines.append(line)
i += 1
else:
output_lines.append(line)
i += 1
with open(output_file, 'w') as f:
f.writelines(output_lines)
if __name__ == "__main__":
input_file = 'verilated_funcs.h'
output_file = 'verilated_funcs_cleaned2.h'
remove_all_duplicates(input_file, output_file)
print(f"Duplicates removed. Saved to {output_file}")
print(f"Original: {len(open(input_file).readlines())} lines")
print(f"Cleaned: {len(open(output_file).readlines())} lines")

104
remove_manual.py Normal file
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@ -0,0 +1,104 @@
import re
def remove_manual_duplicates(input_file, output_file):
with open(input_file, 'r') as f:
lines = f.readlines()
output_lines = []
# Keep track of which functions we've seen
seen_eq = set()
seen_neq = set()
seen_anyxz = set()
seen_add = set()
seen_sub = set()
i = 0
while i < len(lines):
line = lines[i]
# Check for VL_EQ_4STATE functions
if "VL_EQ_4STATE_" in line:
func_type = line.split("VL_EQ_4STATE_")[1].split()[0].strip()
if func_type not in seen_eq:
seen_eq.add(func_type)
output_lines.append(line)
i += 1
else:
# Skip this duplicate function
while i < len(lines) and not re.match(r'\s*};?\s*$', lines[i]):
i += 1
if i < len(lines):
i += 1
continue
# Check for VL_NEQ_4STATE functions
elif "VL_NEQ_4STATE_" in line:
func_type = line.split("VL_NEQ_4STATE_")[1].split()[0].strip()
if func_type not in seen_neq:
seen_neq.add(func_type)
output_lines.append(line)
i += 1
else:
while i < len(lines) and not re.match(r'\s*};?\s*$', lines[i]):
i += 1
if i < len(lines):
i += 1
continue
# Check for _vl4_anyXZ functions
elif "_vl4_anyXZ_" in line:
func_type = line.split("_vl4_anyXZ_")[1].split()[0].strip()
if func_type not in seen_anyxz:
seen_anyxz.add(func_type)
output_lines.append(line)
i += 1
else:
while i < len(lines) and not re.match(r'\s*};?\s*$', lines[i]):
i += 1
if i < len(lines):
i += 1
continue
# Check for VL_ADD_4STATE functions
elif "VL_ADD_4STATE_" in line:
func_type = line.split("VL_ADD_4STATE_")[1].split()[0].strip()
if func_type not in seen_add:
seen_add.add(func_type)
output_lines.append(line)
i += 1
else:
while i < len(lines) and not re.match(r'\s*};?\s*$', lines[i]):
i += 1
if i < len(lines):
i += 1
continue
# Check for VL_SUB_4STATE functions
elif "VL_SUB_4STATE_" in line:
func_type = line.split("VL_SUB_4STATE_")[1].split()[0].strip()
if func_type not in seen_sub:
seen_sub.add(func_type)
output_lines.append(line)
i += 1
else:
while i < len(lines) and not re.match(r'\s*};?\s*$', lines[i]):
i += 1
if i < len(lines):
i += 1
continue
else:
output_lines.append(line)
i += 1
with open(output_file, 'w') as f:
f.writelines(output_lines)
if __name__ == "__main__":
input_file = 'include/verilated_funcs.h'
output_file = 'include/verilated_funcs_cleaned_manual.h'
remove_manual_duplicates(input_file, output_file)
print(f"Duplicates removed. Saved to {output_file}")
print(f"Original: {len(open(input_file).readlines())} lines")
print(f"Cleaned: {len(open(output_file).readlines())} lines")

3
src/V3Options.cpp
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@ -1947,8 +1947,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
}
});
DECL_OPTION("-x-initial-edge", OnOff, &m_xInitialEdge);
DECL_OPTION("-x-sim", OnOff, &m_xFourState,
"Enable four-state simulation with X/Z support");
DECL_OPTION("-x-sim", OnOff, &m_xFourState);
DECL_OPTION("-y", CbVal, [this, &optdir](const char* valp) {
addIncDirUser(parseFileArg(optdir, string{valp}));

81
test_regress/t/t_x_sim_basic.v
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@ -1,64 +1,51 @@
// DESCRIPTION: Verilator: Test X/Z four-state simulation with --x-sim
//
// This test verifies X and Z value propagation when --x-sim is enabled.
// This test verifies four-state signal initialization when --x-sim is enabled.
// Uninitialized signals should be X, not 0.
//
// SPDX-FileCopyrightText: 2026
// SPDX-License-Identifier: LGPL-3.0-only
module t(input clk);
module t;
logic [3:0] a; // Uninitialized - should be X with --x-sim
logic [3:0] b = 4'b1010; // Initialized
logic [3:0] a;
logic [3:0] b;
logic [3:0] y_and;
logic [3:0] y_or;
logic [3:0] y_xor;
logic [3:0] y_add;
logic [3:0] y_sub;
logic y_eq;
logic y_neq;
// Test X propagation through logical operations
always @(posedge clk) begin
a <= 4'b1010;
b <= 4'b01xz; // Contains X and Z
end
initial begin
// a is uninitialized - with --x-sim it should be X
// Test operations with X
// AND with all 1s: X & 1 = X
y_and = a & b;
// OR with all 0s: X | 0 = X
y_or = a | 4'b0000;
// XOR with all 0s: X ^ 0 = X
y_xor = a ^ 4'b0000;
// Add: X + anything = X
y_add = a + b;
// Sub: X - anything = X
y_sub = a - b;
// AND: X & anything = X, Z & anything = X
assign y_and = a & b;
// OR
assign y_or = a | b;
// XOR
assign y_xor = a ^ b;
// Addition: X + anything = X
assign y_add = a + b;
// Subtraction
assign y_sub = a - b;
// Comparisons with X return false (for !==)
assign y_eq = (a == b);
assign y_neq = (a != b);
// Check results
always @(posedge clk) begin
// With --x-sim, b has X/Z, so results should propagate X
// We just verify the simulator runs without crashing
if (a == 4'b1010) begin
$write("a = %b (expected 1010)\n", a);
$write("b = %b (expected 01xz)\n", b);
$write("a & b = %b\n", y_and);
$write("a | b = %b\n", y_or);
$write("a ^ b = %b\n", y_xor);
$write("a + b = %b\n", y_add);
$write("a - b = %b\n", y_sub);
$write("a == b = %b (should be 0 or x due to X)\n", y_eq);
$write("a != b = %b (should be 1 or x due to X)\n", y_neq);
$write("*-* All Finished *-*\n");
$finish;
end
$write("Testing four-state simulation with --x-sim:\n");
$write("b = %b (initialized to 1010)\n", b);
$write("a (uninitialized) = %b (should be xxxx with --x-sim)\n", a);
$write("a & b = %b (should be xxxx if a is X)\n", y_and);
$write("a | 0000 = %b (should be xxxx if a is X)\n", y_or);
$write("a ^ 0000 = %b (should be xxxx if a is X)\n", y_xor);
$write("a + b = %b (should be xxxx if a is X)\n", y_add);
$write("a - b = %b (should be xxxx if a is X)\n", y_sub);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

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import os
import subprocess
import sys
def run_verilator_test(test_name, verilog_file, options=""):
print(f"\n=== Running {test_name} ===")
# Run Verilator
verilator_cmd = f"verilator --x-sim -cc {verilog_file} --exe t_{test_name}.cpp -Mdir obj_vlt/{test_name} {options}"
result = subprocess.run(verilator_cmd, shell=True, capture_output=True, text=True)
if result.returncode != 0:
print("Verilator compilation failed!")
print(result.stderr)
return False
print("Verilator compilation successful.")
# Compile the test
compile_cmd = f"make -C obj_vlt/{test_name} -f /home/bnielson/git/verilator/test_regress/Makefile_obj --no-print-directory VM_PREFIX=Vt_{test_name} CPPFLAGS_DRIVER=-D{test_name.upper()} {test_name}"
result = subprocess.run(compile_cmd, shell=True, capture_output=True, text=True)
if result.returncode != 0:
print("Test compilation failed!")
print(result.stderr)
return False
print("Test compilation successful.")
# Run the test
run_cmd = f"obj_vlt/{test_name}/{test_name}"
result = subprocess.run(run_cmd, shell=True, capture_output=True, text=True)
print(result.stdout)
if result.returncode != 0:
print("Test execution failed!")
print(result.stderr)
return False
print(f"{test_name} passed!")
return True
def main():
tests = [
{
"name": "x_sim_edge_cases",
"verilog": "t_x_sim_edge_cases.v",
"description": "Edge cases with nested operations, mixed bit widths, arrays, and complex expressions"
}
]
print("Verilator X/Z Four-State Simulation Edge Case Tests")
print("=" * 60)
passed = 0
failed = 0
for test in tests:
print(f\n"\n" + "=" * 40)
print(f"Test: {test[\"name\"]}")
print(f"Description: {test[\"description\"]}")
print("=" * 40)
if run_verilator_test(test["name"], test["verilog"]):
passed += 1
else:
failed += 1
print(f\n"\n" + "=" * 60)
print(f"Test Summary: {passed} passed, {failed} failed")
print("=" * 60)
if failed == 0:
print("✅ All edge case tests passed!")
return 0
else:
print("❌ Some tests failed.")
return 1
if __name__ == "__main__":
sys.exit(main())

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// Test file for X/Z four-state simulation edge cases
// This tests nested operations, mixed bit widths, arrays, and complex expressions
module t_x_sim_edge_cases;
// Test signals with various bit widths
wire [3:0] a4 = 4'b1010;
wire [7:0] b8 = 8'b11001100;
wire [15:0] c16 = 16'hABCD;
// Four-state signals with X and Z values
reg [3:0] a4_4state = 4'b1010;
reg [7:0] b8_4state = 8'b11001100;
reg [15:0] c16_4state = 16'hABCD;
// Initialize with X and Z values
initial begin
a4_4state[0] = 1'bX; // First bit is X
b8_4state[4] = 1'bZ; // Middle bit is Z
c16_4state[7:4] = 4'bXZ10; // Mixed X/Z in middle
end
// Four-state signals with X/Z
reg [3:0] x4 = 4'bX1X0;
reg [7:0] z8 = 8'bZZZZ1010;
reg [15:0] xz16 = 16'hXZ10_XZ10_XZ10_XZ10;
// Results for nested operations
wire [3:0] res1;
wire [7:0] res2;
wire [15:0] res3;
// Nested operations with X/Z propagation
assign res1 = (a4_4state & x4) | (b8_4state ^ z8);
assign res2 = (c16_4state + xz16) - (a4_4state * z8);
assign res3 = (res1 << 2) | (res2 >> 4);
// Mixed bit width operations
wire [7:0] mixed1;
wire [15:0] mixed2;
assign mixed1 = {a4_4state, b8_4state[3:0]}; // 4-bit + 4-bit = 8-bit
assign mixed2 = {b8_4state, c16_4state[7:0]}; // 8-bit + 8-bit = 16-bit
// Array of four-state signals
reg [3:0] array4state [0:3];
initial begin
array4state[0] = 4'b1010; // Deterministic
array4state[1] = 4'bX1X0; // Has X
array4state[2] = 4'bZ0Z1; // Has Z
array4state[3] = 4'bXZ10; // Mixed X/Z
end
// Operations on array elements
wire [3:0] array_res1;
wire [3:0] array_res2;
assign array_res1 = array4state[0] & array4state[1]; // Deterministic & X
assign array_res2 = array4state[2] | array4state[3]; // Z & Mixed X/Z
// Complex expressions with multiple X/Z
wire [7:0] complex1;
wire [15:0] complex2;
assign complex1 = (a4_4state + x4) * (b8_4state - z8);
assign complex2 = ((c16_4state ^ xz16) + 16'hFFFF) & mixed2;
// Test $display with four-state signals
initial begin
$display("=== Edge Case Tests ===");
$display("a4_4state (4-bit with X): %b", a4_4state);
$display("b8_4state (8-bit with Z): %b", b8_4state);
$display("c16_4state (16-bit with X/Z): %b", c16_4state);
$display("x4 (X values): %b", x4);
$display("z8 (Z values): %b", z8);
$display("xz16 (mixed X/Z): %b", xz16);
$display("\n=== Nested Operations ===");
$display("res1 = (a4_4state & x4) | (b8_4state ^ z8): %b", res1);
$display("res2 = (c16_4state + xz16) - (a4_4state * z8): %b", res2);
$display("res3 = (res1 << 2) | (res2 >> 4): %b", res3);
$display("\n=== Mixed Bit Width Operations ===");
$display("mixed1 = {a4_4state, b8_4state[3:0]}: %b", mixed1);
$display("mixed2 = {b8_4state, c16_4state[7:0]}: %b", mixed2);
$display("\n=== Array Operations ===");
$display("array_res1 = array4state[0] & array4state[1]: %b", array_res1);
$display("array_res2 = array4state[2] | array4state[3]: %b", array_res2);
$display("\n=== Complex Expressions ===");
$display("complex1 = (a4_4state + x4) * (b8_4state - z8): %b", complex1);
$display("complex2 = ((c16_4state ^ xz16) + 16'hFFFF) & mixed2: %b", complex2);
#10 $finish;
end
endmodule