Commentary: Changes update

Changes

@@ -1,5 +1,7 @@
 .. for github, vim: syntax=reStructuredText
 
+.. Maintainers and agents, do not edit this file, it will be updated for you post- PR-merge.
+
 ===============================
 Revision History and Change Log
 ===============================
@@ -38,17 +40,25 @@ Verilator 5.049 devel
 * Support streaming on queues (#7597). [Benjamin Collier, Secturion Systems, Inc.]
 * Support FSM detection in primitive wrappers (#7607). [Yogish Sekhar]
 * Support busses with mix of pullup/pulldown (#7632). [Lucas Amaral]
+* Support pre/post increment/decrement inside && and || (#7683). [Nick Brereton]
+* Add `+verilator+log+file` (#4505) (#7645). [Tracy Narine]
 * Add peak memory usage to `--stats`. [Geza Lore, Testorrent USA, Inc.]
 * Add error on mixed-initialization (#7352) (#7357).
+* Add `--coverage-per-instance` (#7636). [Yogish Sekhar]
+* Add NOTREDOP error on reduction and negation operators (#7417) (#7623) (#7624).
 * Improve `--coverage-fsm` (#7490) (#7529) (#7561) (#7573) (#7619). [Yogish Sekhar]
 * Change `+verilator+seed` to default to 1, and 0 to randomly select (#7325) (#7516). [Miguel]
 * Change JSON to include parameter constant mnemonics for FSM Coverage (#7531). [Yogish Sekhar]
 * Optimize emitting to_string() for compiler speedup (#7468). [Jakub Michalski, Antmicro Ltd.]
 * Optimize additional DFG peephole cases (#7553). [Varun Koyyalagunta, Testorrent USA, Inc.]
 * Optimize forced signal handling (#7554 partial) (#7572) (#7594) (#7596). [Krzysztof Bieganski, Artur Bieniek, Antmicro Ltd.]
+* Optimize primitive runtime functions. [Geza Lore, Testorrent USA, Inc.]
+* Optimize if branches with same trailing statements (#7674). [Geza Lore, Testorrent USA, Inc.]
 * Fix inlining static initializer in V3Gate (#5381) (#7503). [Andrew Nolte] [Geza Lore, Testorrent USA, Inc.]
 * Fix segmentation fault when using --trace with --lib-create (#7299) (#7518). [anonkey]
 * Fix destructive event state before dynamic waits (#7340). [Nick Brereton]
+* Fix ALWCOMBORDER on variable ordering (#7350) (#7608). [Cookie]
+* Fix false MULTIDRIVEN warning on always_ff variables (#7351) (#7621) (#7672).
 * Fix array pattern concatenation (#7401) (#7402). [Greg Davill]
 * Fix fairness in `std::semaphore` (#7435) (#7605). [Krzysztof Bieganski, Antmicro Ltd.]
 * Fix generic interface port forwarded to a nested instance (#7454) (#7457). [Yilou Wang]
@@ -63,27 +73,41 @@ Verilator 5.049 devel
 * Fix $bits on local struct with chained-interface (#7515) (#7517).
 * Fix array indexing side effects in compound assignments (#7519) (#7540) (#7544). [Kamil Danecki, Antmicro Ltd.]
 * Fix class::localparam during elaboration (#7524) (#7534).
+* Fix dearray variable scope error (#7530) (#7602).
 * Fix nested parameterized class typedef chain (#7538). [Michael Rogenmoser]
 * Fix events in observed region (#7546). [Todd Strader]
 * Fix regression rejecting boolean `!x` inside sequence expressions (#7549) (#7551). [Yilou Wang]
 * Fix exponential expansion in V3Gate (#7550). [Geza Lore, Testorrent USA, Inc.]
 * Fix internal error on consecutive repetition with N > 256 (#7552) (#7603). [Yilou Wang]
+* Fix inherited rand array with .size + foreach constraint (#7558) (#7650). [Yilou Wang]
+* Fix biased bit distribution under value < (1 << N) constraints (#7563) (#7684). [Yilou Wang]
 * Fix display of %m in non-first argument (#7574).
 * Fix floating point compile warning on min/max delays.
 * Fix force of unpacked arrays (#7579) (#7580). [Zubin Jain]
 * Fix property argument retaining type of the previous variable (#7582). [Jakub Michalski]
 * Fix NBA to whole arrays (#7583) (#7575). [Geza Lore, Testorrent USA, Inc.]
+* Fix wrong false assert for property local variables with cycle-delayed consequents (#7587) (#7651). [Yilou Wang]
 * Fix interface instance name collision (#7591) (#7593). [Stuart Morris]
 * Fix process comparison compile error with `--public-flat-rw` (#7592).
 * Fix CPU pinning when no 'core id' present (#7599). [Geza Lore, Testorrent USA, Inc.]
+* Fix access to parameters via class::localparam (#7609) (#7671). [em2machine]
 * Fix clocking-block sample of unpacked array (#7612) (#7613). [Nikolai Kumar]
 * Fix type parameters order (#7615). [Kamil Danecki, Antmicro Ltd.]
 * Fix unique_index method on assoc arrays with values differing from the keys (#7616). [Pawel Klopotek]
 * Fix wide equality comparison in unpacked structs (#7618). [Geza Lore, Testorrent USA, Inc.]
 * Fix force determinism (#7620) (#7637). [Artur Bieniek, Antmicro Ltd.]
 * Fix reference counting for modport task references (#7628). [Nick Brereton]
+* Fix internal error when handling typedefs containing parameterized class type members (#7635) (#7661). [em2machine]
+* Fix forceable signal with a procedural continuous assign (#7638) (#7639). [Zubin Jain]
 * Fix implicit conversions of VlWide (#7642). [Geza Lore, Testorrent USA, Inc.]
 * Fix CASEINCOMPLETE to not warn on `unique0 case` (#7647).
+* Fix hierarchical coverage counts for duplicate no-inline module instances (#7649). [Yogish Sekhar]
+* Fix dropped iff guard on clocking inside task (#7658) (#7659). [Nikolai Kumar]
+* Fix runtime speed summary report. [Geza Lore, Testorrent USA, Inc.]
+* Fix reserved keywords reaching emitter (#7666). [Pawel Kojma, Antmicro Ltd.]
+* Fix width of unsized literal in property expression (#7668). [Artur Bieniek, Antmicro Ltd.]
+* Fix loss of events due to bit shift (#7670). [Artur Bieniek, Antmicro Ltd.]
+* Fix parameter read through locally-declared interface instance (#7679). [Nick Brereton]
 
 
 Verilator 5.048 2026-04-26
@@ -2420,7 +2444,6 @@ Verilator 4.108 2021-01-10
 * Fix to ignore coverage on real ports (#2741) (#2745). [Paul Wright]
 
 
-
 Verilator 4.106 2020-12-02
 ==========================
 
@@ -2827,7 +2850,6 @@ Verilator 4.018 2019-08-29
 * Fix internal error on gate optimization of assign. (#1475) [Oyvind Harboe]
 
 
-
 Verilator 4.016 2019-06-16
 ==========================
 
@@ -5278,7 +5300,6 @@ Verilator 3.270 2004-10-15
 * Fix numeric fault when dividing by zero.
 
 
-
 Verilator 3.260 2004-10-07
 ==========================
 

docs/guide/install.rst

@@ -170,6 +170,9 @@ once, after ``configure``:
 
 .. code-block:: bash
 
+   # Install dependencies
+   sudo apt install python3-pip
+
    # Create Python virutal environment in .venv:
    make venv
 

docs/spelling.txt

@@ -670,6 +670,7 @@ concatenatable
 concats
 conf
 config
+consequents
 const
 constexpr
 constification
@@ -701,6 +702,7 @@ datafiles
 david
 ddd
 de
+dearray
 deassign
 debugi
 defenv
@@ -1214,6 +1216,7 @@ unnamedblk
 unopt
 unoptflat
 unoptimizable
+unparenthesized
 unroller
 unsatisfiable
 unsized

test_regress/t/t_assert_property_unsized.v

@@ -4,14 +4,14 @@
 // SPDX-FileCopyrightText: 2026 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-module t(
-  input clk
+module t (
+    input clk
 );
 
   localparam MAX = 15;
   integer cyc = 0;
 
-  assert property (@(posedge clk) always[1:2] 1);
+  assert property (@(posedge clk) always[1: 2] 1);
 
   always @(clk) begin
     ++cyc;

test_regress/t/t_class_lparam_chain.v

@@ -17,23 +17,25 @@
 // verilog_format: on
 
 module t;
-  virtual class C #(parameter int a);
+  virtual class C #(
+      parameter int a
+  );
     localparam int b = a;
   endclass
 
-  typedef C#(0)  inst0;
+  typedef C#(0) inst0;
   typedef C#(42) inst42;
 
   // Direct: inst::b Dot in the value
-  localparam int b0  = inst0::b;
+  localparam int b0 = inst0::b;
   localparam int b42 = inst42::b;
 
   // One-step chain: refers to a deferred lparam
-  localparam int c0  = b0;
+  localparam int c0 = b0;
   localparam int c42 = b42;
 
   // Multi-step chain: d -> c -> b -> inst::b
-  localparam int d0  = c0;
+  localparam int d0 = c0;
   localparam int d42 = c42;
 
   // Expression referencing two deferred lparams

test_regress/t/t_clocking_iff_class.v

@@ -15,14 +15,22 @@ module t;
   monitor mon = new;
   always #5 mon.clk = ~mon.clk;
   initial begin
-    fork mon.run(); join_none
+    fork
+      mon.run();
+    join_none
 
-    repeat(4) @(posedge mon.clk);
-    if (mon.fired !== 0) begin $display("FAIL: fired before iff guard satisfied"); $stop; end
+    repeat (4) @(posedge mon.clk);
+    if (mon.fired !== 0) begin
+      $display("FAIL: fired before iff guard satisfied");
+      $stop;
+    end
 
     mon.enable = 1;
     repeat (2) @(posedge mon.clk);
-    if (mon.fired !== 1) begin $display("FAIL: did not fire when guard true"); $stop; end
+    if (mon.fired !== 1) begin
+      $display("FAIL: did not fire when guard true");
+      $stop;
+    end
     $write("*-* All Finished *-*\n");
     $finish;
   end

test_regress/t/t_cover_hier.out

@@ -1,6 +1,6 @@
 # SystemC::Coverage-3
-C '
ft/t_cover_hier.v
l19
n5
tuser
pagev_user/child
osame_stmt
S19
htop.t.u_a.same_stmt' 4
-C '
ft/t_cover_hier.v
l19
n5
tuser
pagev_user/child
osame_stmt
S19
htop.t.u_b.same_stmt' 1
+C '
ft/t_cover_hier.v
l19
n3
tuser
pagev_user/child
osame_stmt
S19
htop.t.u_a.same_stmt' 4
+C '
ft/t_cover_hier.v
l19
n3
tuser
pagev_user/child
osame_stmt
S19
htop.t.u_b.same_stmt' 1
 C '
ft/t_cover_hier.v
l21
n3
tline
pagev_line/child
oblock
S21
htop.t.u_a' 9
 C '
ft/t_cover_hier.v
l21
n3
tline
pagev_line/child
oblock
S21
htop.t.u_b' 9
 C '
ft/t_cover_hier.v
l22
n5
tbranch
pagev_branch/child
oif
S22
htop.t.u_a' 4

test_regress/t/t_cover_hier.v

@@ -15,8 +15,8 @@ module child (
 
   // The user cover and generated line/branch coverage below share one
   // module body but must produce independent counters per instance.
-  same_stmt:
-    cover property (@(posedge clk) en);
+  same_stmt :
+  cover property (@(posedge clk) en);
 
   always @(posedge clk) begin
     if (en) seen <= 1'b1;

test_regress/t/t_cover_per_instance.dat.out

@@ -8,13 +8,13 @@ C '
ft/t_cover_per_instance.v
l18
n3
tline
pagev_line/child__W3
oblock
S1
 C '
ft/t_cover_per_instance.v
l19
n5
tbranch
pagev_branch/child
oif
S19-20
htb.dut.u_a' 4
 C '
ft/t_cover_per_instance.v
l19
n5
tbranch
pagev_branch/child
oif
S19-20
htb.dut.u_b' 1
 C '
ft/t_cover_per_instance.v
l19
n5
tbranch
pagev_branch/child__W3
oif
S19-20
htb.dut.u_wide' 2
-C '
ft/t_cover_per_instance.v
l19
n6
tbranch
pagev_branch/child
oelse
S21-22
htb.dut.u_a' 5
-C '
ft/t_cover_per_instance.v
l19
n6
tbranch
pagev_branch/child
oelse
S21-22
htb.dut.u_b' 8
-C '
ft/t_cover_per_instance.v
l19
n6
tbranch
pagev_branch/child__W3
oelse
S21-22
htb.dut.u_wide' 7
-C '
ft/t_cover_per_instance.v
l30
n19
tline
pagev_line/t
oblock
S30
htb.dut' 1
-C '
ft/t_cover_per_instance.v
l55
n3
tline
pagev_line/t
oblock
S55-56
htb.dut' 9
-C '
ft/t_cover_per_instance.v
l61
n13
tline
pagev_line/tb
oblock
S61
htb' 1
-C '
ft/t_cover_per_instance.v
l67
n3
tline
pagev_line/tb
oblock
S67
htb' 17
-C '
ft/t_cover_per_instance.v
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n3
tline
pagev_line/tb
oblock
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htb' 9
-C '
ft/t_cover_per_instance.v
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n5
tbranch
pagev_branch/tb
oif
S70-72
htb' 1
-C '
ft/t_cover_per_instance.v
l70
n6
tbranch
pagev_branch/tb
oelse
htb' 8
+C '
ft/t_cover_per_instance.v
l19
n6
tbranch
pagev_branch/child
oelse
S22-23
htb.dut.u_a' 5
+C '
ft/t_cover_per_instance.v
l19
n6
tbranch
pagev_branch/child
oelse
S22-23
htb.dut.u_b' 8
+C '
ft/t_cover_per_instance.v
l19
n6
tbranch
pagev_branch/child__W3
oelse
S22-23
htb.dut.u_wide' 7
+C '
ft/t_cover_per_instance.v
l31
n19
tline
pagev_line/t
oblock
S31
htb.dut' 1
+C '
ft/t_cover_per_instance.v
l56
n3
tline
pagev_line/t
oblock
S56-57
htb.dut' 9
+C '
ft/t_cover_per_instance.v
l62
n13
tline
pagev_line/tb
oblock
S62
htb' 1
+C '
ft/t_cover_per_instance.v
l66
n3
tline
pagev_line/tb
oblock
S66
htb' 17
+C '
ft/t_cover_per_instance.v
l68
n3
tline
pagev_line/tb
oblock
S68
htb' 9
+C '
ft/t_cover_per_instance.v
l69
n5
tbranch
pagev_branch/tb
oif
S69-71
htb' 1
+C '
ft/t_cover_per_instance.v
l69
n6
tbranch
pagev_branch/tb
oelse
htb' 8

test_regress/t/t_cover_per_instance.out

@@ -34,7 +34,8 @@
 -000004  point: type=branch comment=if hier=tb.dut.u_a
 -000001  point: type=branch comment=if hier=tb.dut.u_b
 -000002  point: type=branch comment=if hier=tb.dut.u_wide
-%000008     end else begin
+            end
+%000008     else begin
 -000005  point: type=branch comment=else hier=tb.dut.u_a
 -000008  point: type=branch comment=else hier=tb.dut.u_b
 -000007  point: type=branch comment=else hier=tb.dut.u_wide
@@ -86,9 +87,7 @@
 %000001   reg clk = 0;
 -000001  point: type=line comment=block hier=tb
         
-          t dut (
-              .clk(clk)
-          );
+          t dut (.clk(clk));
         
  000017   always #1 clk = !clk;
 +000017  point: type=line comment=block hier=tb

test_regress/t/t_cover_per_instance.v

@@ -18,7 +18,8 @@ module child #(
   always @(posedge clk) begin
     if (en) begin
       count <= count + 1'b1;
-    end else begin
+    end
+    else begin
       count <= count;
     end
   end
@@ -60,9 +61,7 @@ endmodule
 module tb;
   reg clk = 0;
 
-  t dut (
-      .clk(clk)
-  );
+  t dut (.clk(clk));
 
   always #1 clk = !clk;
 

test_regress/t/t_cover_per_instance_user.out

@@ -23,35 +23,35 @@ C '
ft/t_cover_per_instance_user.v
l12
n13
ttoggle
pagev_toggle/child
ocou
 C '
ft/t_cover_per_instance_user.v
l12
n13
ttoggle
pagev_toggle/child
ocount[3]:1->0
htb.wrap_b.dut_b' 0
 C '
ft/t_cover_per_instance_user.v
l12
n21
tline
pagev_line/child
oblock
S12
htb.dut_a' 1
 C '
ft/t_cover_per_instance_user.v
l12
n21
tline
pagev_line/child
oblock
S12
htb.wrap_b.dut_b' 1
-C '
ft/t_cover_per_instance_user.v
l15
n5
tuser
pagev_user/child
osame_stmt
S15
htb.dut_a.same_stmt' 4
-C '
ft/t_cover_per_instance_user.v
l15
n5
tuser
pagev_user/child
osame_stmt
S15
htb.wrap_b.dut_b.same_stmt' 1
+C '
ft/t_cover_per_instance_user.v
l15
n3
tuser
pagev_user/child
osame_stmt
S15
htb.dut_a.same_stmt' 4
+C '
ft/t_cover_per_instance_user.v
l15
n3
tuser
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osame_stmt
S15
htb.wrap_b.dut_b.same_stmt' 1
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ft/t_cover_per_instance_user.v
l17
n3
tline
pagev_line/child
oblock
S17-18
htb.dut_a' 9
 C '
ft/t_cover_per_instance_user.v
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tline
pagev_line/child
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htb.wrap_b.dut_b' 1
-C '
ft/t_cover_per_instance_user.v
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tbranch
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oelse
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-C '
ft/t_cover_per_instance_user.v
l19
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oelse
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-C '
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oclk:0->1
htb.wrap_b' 9
-C '
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oclk:1->0
htb.wrap_b' 8
-C '
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oen:0->1
htb.wrap_b' 1
-C '
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oen:1->0
htb.wrap_b' 1
-C '
ft/t_cover_per_instance_user.v
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oblock
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htb' 1
-C '
ft/t_cover_per_instance_user.v
l38
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oclk:0->1
htb' 9
-C '
ft/t_cover_per_instance_user.v
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oclk:1->0
htb' 8
-C '
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ocyc[0]:0->1
htb' 5
-C '
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ocyc[0]:1->0
htb' 4
-C '
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-C '
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htb' 2
-C '
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ocyc[2]:0->1
htb' 1
-C '
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l39
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ocyc[2]:1->0
htb' 1
-C '
ft/t_cover_per_instance_user.v
l39
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ocyc[3]:0->1
htb' 1
-C '
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ocyc[3]:1->0
htb' 0
-C '
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-C '
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htb' 9
-C '
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-C '
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-C '
ft/t_cover_per_instance_user.v
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oif
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htb' 1
-C '
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oelse
htb' 8
+C '
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l19
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tbranch
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oelse
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+C '
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l19
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tbranch
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+C '
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l29
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oclk:0->1
htb.wrap_b' 9
+C '
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l29
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oclk:1->0
htb.wrap_b' 8
+C '
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l30
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oen:0->1
htb.wrap_b' 1
+C '
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l30
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oen:1->0
htb.wrap_b' 1
+C '
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oblock
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+C '
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oclk:0->1
htb' 9
+C '
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htb' 8
+C '
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ocyc[0]:0->1
htb' 5
+C '
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+C '
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test_regress/t/t_cover_per_instance_user.v

@@ -11,14 +11,15 @@ module child (
   reg observed = 1'b0;
   reg [3:0] count = 0;
 
-  same_stmt:
-    cover property (@(posedge clk) en);
+  same_stmt :
+  cover property (@(posedge clk) en);
 
   always @(posedge clk) begin
     observed <= en;
     if (en) begin
       count <= count + 1'b1;
-    end else begin
+    end
+    else begin
       count <= count;
     end
   end

test_regress/t/t_forceable_assigncont.v

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t;
-  logic forceable_q /*verilator forceable*/ = 1'b0;
+  logic forceable_q  /*verilator forceable*/ = 1'b0;
   logic assigned_q = 1'b0;
 
   // Regression for V3Force: assignAll() should reuse the helper vars created by

test_regress/t/t_fork_join_none_wait_ev.v

@@ -9,8 +9,8 @@
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-module t(
-  input clk
+module t (
+    input clk
 );
   int cyc = 0;
   int cnt = 0;

test_regress/t/t_interface_modport_param.v

@@ -21,9 +21,7 @@ module pass_through (
     intf.source in_port,
     output logic [31:0] item_qty
 );
-  intf #(
-      .ITEM_QTY(in_port.ITEM_QTY)
-  ) internal_port ();
+  intf #(.ITEM_QTY(in_port.ITEM_QTY)) internal_port ();
 
   if (internal_port.ITEM_QTY == 1) begin : g_saw_default_item_qty
     $error("generate if evaluated internal_port.ITEM_QTY as interface default 1");
@@ -37,16 +35,14 @@ module pass_through (
 endmodule
 
 module t;
-  intf #(
-      .ITEM_QTY(20)
-  ) in_port ();
+  intf #(.ITEM_QTY(20)) in_port ();
 
   logic [31:0] item_qty;
 
   assign in_port.item = 1'b0;
 
   pass_through dut (
-      .in_port (in_port),
+      .in_port(in_port),
       .item_qty(item_qty)
   );
 

test_regress/t/t_lint_always_comb_order_bad.out

@@ -3,15 +3,15 @@
                        t/t_lint_always_comb_order_bad.v:23:19: ... Location of earlier read
    23 |     result1 = a + accum1;
       |                   ^~~~~~
-   24 |     accum1  = b;
+   24 |     accum1 = b;
       |     ^~~~~~
                        ... For warning description see https://verilator.org/warn/ALWCOMBORDER?v=latest
                        ... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message.
-%Warning-ALWCOMBORDER: t/t_lint_always_comb_order_bad.v:44:5: always_comb reads 'accum3' before assigning it later in the same block; behavior may imply latch/state-like behavior and is not purely combinational
+%Warning-ALWCOMBORDER: t/t_lint_always_comb_order_bad.v:45:5: always_comb reads 'accum3' before assigning it later in the same block; behavior may imply latch/state-like behavior and is not purely combinational
                                                             : ... note: In instance 't'
                        t/t_lint_always_comb_order_bad.v:40:21: ... Location of earlier read
    40 |       result3 = a + accum3;
       |                     ^~~~~~
-   44 |     accum3 = b;
+   45 |     accum3 = b;
       |     ^~~~~~
 %Error: Exiting due to

test_regress/t/t_lint_always_comb_order_bad.v

@@ -5,10 +5,10 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-    input  logic [3:0] a,
-    input  logic [3:0] b,
-    input  logic [3:0] c,
-    input  logic       sel,
+    input logic [3:0] a,
+    input logic [3:0] b,
+    input logic [3:0] c,
+    input logic sel,
     output logic [3:0] result1,
     output logic [3:0] result2,
     output logic [3:0] result3,
@@ -21,11 +21,11 @@ module t (
 
   always_comb begin
     result1 = a + accum1;
-    accum1  = b;
+    accum1 = b;
   end
 
   always_comb begin
-    accum2  = b;
+    accum2 = b;
     result2 = a + accum2;  // write-before-read: do not warn
   end
 
@@ -38,7 +38,8 @@ module t (
   always_comb begin
     if (sel) begin
       result3 = a + accum3;
-    end else begin
+    end
+    else begin
       result3 = c;
     end
     accum3 = b;

test_regress/t/t_lint_notredop_bad.v

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-    input  logic [3:0] v,
+    input logic [3:0] v,
     output logic [6:0] y
 );
 

test_regress/t/t_math_postinc.v

@@ -14,169 +14,169 @@
 // verilog_format: on
 
 module t;
-   integer a, b, c;
-   reg cond;
-   int side;
+  integer a, b, c;
+  reg cond;
+  int side;
 
-   // Impure (side-effecting) function for use as a short-circuit LHS
-   function automatic int bump();
-      side = side + 1;
-      return 1;
-   endfunction
+  // Impure (side-effecting) function for use as a short-circuit LHS
+  function automatic int bump();
+    side = side + 1;
+    return 1;
+  endfunction
 
-   // ++/-- in && / || inside a function/task exercises the function-local temp
-   function automatic int f_and(int x);
-      if (x > 0 && x++ < 100) ;
-      return x;
-   endfunction
-   function automatic int f_or(int x);
-      if (x > 0 || x++ < 100) ;
-      return x;
-   endfunction
-   // LHS reads the gated variable; must see the pre-increment value exactly once
-   function automatic int f_single(int x);
-      int taken = 0;
-      if (x == 4 && x++ < 100) taken = 1;
-      return taken * 1000 + x;
-   endfunction
+  // ++/-- in && / || inside a function/task exercises the function-local temp
+  function automatic int f_and(int x);
+    if (x > 0 && x++ < 100) ;
+    return x;
+  endfunction
+  function automatic int f_or(int x);
+    if (x > 0 || x++ < 100) ;
+    return x;
+  endfunction
+  // LHS reads the gated variable; must see the pre-increment value exactly once
+  function automatic int f_single(int x);
+    int taken = 0;
+    if (x == 4 && x++ < 100) taken = 1;
+    return taken * 1000 + x;
+  endfunction
 
-   initial begin
-      // ---- Basic post/pre increment/decrement ----
-      a = 5;   b = a++;            `checkh(b, 5);   `checkh(a, 6);
-      a = 5;   b = ++a;            `checkh(a, 6);   `checkh(b, 6);
-      a = 10;  b = 5;   b = a++ + b; `checkh(b, 15); `checkh(a, 11);
-      a = 10;  b = 5;   b = ++a + b; `checkh(b, 16); `checkh(a, 11);
-      a = 7;   b = a++ * 2;        `checkh(b, 14);  `checkh(a, 8);
-      a = 7;   b = ++a * 2;        `checkh(b, 16);  `checkh(a, 8);
-      a = 3;   b = 4;   c = a++ + b++; `checkh(c, 7);  `checkh(a, 4); `checkh(b, 5);
-      a = 3;   b = 4;   c = ++a + ++b; `checkh(c, 9);  `checkh(a, 4); `checkh(b, 5);
-      a = 10;  b = 3;   c = a++ - b--; `checkh(c, 7);  `checkh(a, 11); `checkh(b, 2);
-      a = 5;   b = 5;   b = a--;      `checkh(b, 5);  `checkh(a, 4);
-      a = 5;   b = --a;               `checkh(b, 4);  `checkh(a, 4);
+  initial begin
+    // ---- Basic post/pre increment/decrement ----
+    a = 5;  b = a++;        `checkh(b, 5);  `checkh(a, 6);
+    a = 5;  b = ++a;        `checkh(a, 6);  `checkh(b, 6);
+    a = 10;  b = 5;  b = a++ + b; `checkh(b, 15); `checkh(a, 11);
+    a = 10;  b = 5;  b = ++a + b; `checkh(b, 16); `checkh(a, 11);
+    a = 7;  b = a++ * 2;      `checkh(b, 14);  `checkh(a, 8);
+    a = 7;  b = ++a * 2;      `checkh(b, 16);  `checkh(a, 8);
+    a = 3;  b = 4;  c = a++ + b++; `checkh(c, 7);  `checkh(a, 4); `checkh(b, 5);
+    a = 3;  b = 4;  c = ++a + ++b; `checkh(c, 9);  `checkh(a, 4); `checkh(b, 5);
+    a = 10;  b = 3;  c = a++ - b--; `checkh(c, 7);  `checkh(a, 11); `checkh(b, 2);
+    a = 5;  b = 5;  b = a--;    `checkh(b, 5);  `checkh(a, 4);
+    a = 5;  b = --a;          `checkh(b, 4);  `checkh(a, 4);
 
-      // ---- Post-inc in shift (5 << 5 = 160) ----
-      a = 5;   b = 5;   b = b << a++; `checkh(b, 160); `checkh(a, 6);
+    // ---- Post-inc in shift (5 << 5 = 160) ----
+    a = 5;  b = 5;  b = b << a++; `checkh(b, 160); `checkh(a, 6);
 
-      // ---- Post-inc in paren expr ----
-      a = 2;   b = (a++ + 1) * 3;     `checkh(b, 9);  `checkh(a, 3);
+    // ---- Post-inc in paren expr ----
+    a = 2;  b = (a++ + 1) * 3;    `checkh(b, 9);  `checkh(a, 3);
 
-      // ---- Post-inc in while with && (constant) ----
-      a = 0;   while (1 && a++ < 3) begin end `checkh(a, 4);
+    // ---- Post-inc in while with && (constant) ----
+    a = 0;  while (1 && a++ < 3) begin end `checkh(a, 4);
 
-      // ---- Post-inc in while with && (variable cond, non-short-circuit) ----
-      cond = 1;   a = 0;   while (cond && a++ < 3) begin end `checkh(a, 4);
+    // ---- Post-inc in while with && (variable cond, non-short-circuit) ----
+    cond = 1;  a = 0;  while (cond && a++ < 3) begin end `checkh(a, 4);
 
-      // ---- Post-inc in while with && (variable cond, short-circuit) ----
-      cond = 0;   a = 0;   while (cond && a++ < 3) begin end `checkh(a, 0);
+    // ---- Post-inc in while with && (variable cond, short-circuit) ----
+    cond = 0;  a = 0;  while (cond && a++ < 3) begin end `checkh(a, 0);
 
-      // ---- Post-inc in while with || ----
-      a = 0;   while (0 || a++ < 3) begin end `checkh(a, 4);
+    // ---- Post-inc in while with || ----
+    a = 0;  while (0 || a++ < 3) begin end `checkh(a, 4);
 
-      // ---- && short-circuit ----
-      a = 0;   if (0 && a++ < 3) begin end    `checkh(a, 0);
+    // ---- && short-circuit ----
+    a = 0;  if (0 && a++ < 3) begin end   `checkh(a, 0);
 
-      // ---- && non-short-circuit ----
-      a = 0;   if (1 && a++ < 5) begin end    `checkh(a, 1);
+    // ---- && non-short-circuit ----
+    a = 0;  if (1 && a++ < 5) begin end   `checkh(a, 1);
 
-      // ---- || non-short-circuit ----
-      a = 0;   if (0 || a++ < 5) begin end    `checkh(a, 1);
+    // ---- || non-short-circuit ----
+    a = 0;  if (0 || a++ < 5) begin end   `checkh(a, 1);
 
-      // ---- || short-circuit ----
-      a = 0;   if (1 || a++ < 5) begin end    `checkh(a, 0);
+    // ---- || short-circuit ----
+    a = 0;  if (1 || a++ < 5) begin end   `checkh(a, 0);
 
-      // ---- Pre-inc with && ----
-      a = 0;   if (1 && ++a < 5) begin end    `checkh(a, 1);
+    // ---- Pre-inc with && ----
+    a = 0;  if (1 && ++a < 5) begin end   `checkh(a, 1);
 
-      // ---- Pre-inc short-circuit ----
-      a = 0;   if (0 && ++a < 5) begin end    `checkh(a, 0);
+    // ---- Pre-inc short-circuit ----
+    a = 0;  if (0 && ++a < 5) begin end   `checkh(a, 0);
 
-      // ---- Pre-inc with || ----
-      a = 0;   if (0 || ++a < 5) begin end    `checkh(a, 1);
-      a = 0;   if (1 || ++a < 5) begin end    `checkh(a, 0);
+    // ---- Pre-inc with || ----
+    a = 0;  if (0 || ++a < 5) begin end   `checkh(a, 1);
+    a = 0;  if (1 || ++a < 5) begin end   `checkh(a, 0);
 
-      // ---- Nested && chain ----
-      a = 0;   if (1 && 1 && a++ < 5) begin end `checkh(a, 1);
+    // ---- Nested && chain ----
+    a = 0;  if (1 && 1 && a++ < 5) begin end `checkh(a, 1);
 
-      // ---- Post-dec with && ----
-      a = 5;   if (1 && a-- > 0) begin end    `checkh(a, 4);
+    // ---- Post-dec with && ----
+    a = 5;  if (1 && a-- > 0) begin end   `checkh(a, 4);
 
-      // ---- Pre-dec with && short-circuit ----
-      a = 5;   if (0 && --a > 0) begin end    `checkh(a, 5);
+    // ---- Pre-dec with && short-circuit ----
+    a = 5;  if (0 && --a > 0) begin end   `checkh(a, 5);
 
-      // ---- Post-dec with || ----
-      a = 5;   if (0 || a-- > 0) begin end    `checkh(a, 4);
-      a = 5;   if (1 || a-- > 0) begin end    `checkh(a, 5);
+    // ---- Post-dec with || ----
+    a = 5;  if (0 || a-- > 0) begin end   `checkh(a, 4);
+    a = 5;  if (1 || a-- > 0) begin end   `checkh(a, 5);
 
-      // ---- Pre-dec with || ----
-      a = 5;   if (0 || --a > 0) begin end    `checkh(a, 4);
+    // ---- Pre-dec with || ----
+    a = 5;  if (0 || --a > 0) begin end   `checkh(a, 4);
 
-      // ---- Multiple increments in && chain ----
-      a = 0;  b = 0;
-      if (1 && a++ < 5 && b++ < 5) begin end
-      `checkh(a, 1);  `checkh(b, 1);
+    // ---- Multiple increments in && chain ----
+    a = 0;  b = 0;
+    if (1 && a++ < 5 && b++ < 5) begin end
+    `checkh(a, 1);  `checkh(b, 1);
 
-      // ---- Post-inc on left side of && ----
-      a = 0;   if (a++ < 5 && 1) begin end    `checkh(a, 1);
+    // ---- Post-inc on left side of && ----
+    a = 0;  if (a++ < 5 && 1) begin end   `checkh(a, 1);
 
-      // ---- Post-inc on left side of || ----
-      a = 0;   if (a++ < 5 || 0) begin end    `checkh(a, 1);
+    // ---- Post-inc on left side of || ----
+    a = 0;  if (a++ < 5 || 0) begin end   `checkh(a, 1);
 
-      // ---- Pre-inc on left side of || ----
-      a = 0;   if (++a < 5 || 0) begin end    `checkh(a, 1);
+    // ---- Pre-inc on left side of || ----
+    a = 0;  if (++a < 5 || 0) begin end   `checkh(a, 1);
 
-      // ---- Mixed && and || with post-inc ----
-      a = 0;  b = 0;
-      if (1 && a++ < 5 || b++ < 5) begin end
-      `checkh(a, 1);  `checkh(b, 0);
+    // ---- Mixed && and || with post-inc ----
+    a = 0;  b = 0;
+    if (1 && a++ < 5 || b++ < 5) begin end
+    `checkh(a, 1);  `checkh(b, 0);
 
-      a = 0;  b = 0;
-      if (0 && a++ < 5 || b++ < 5) begin end
-      `checkh(a, 0);  `checkh(b, 1);
+    a = 0;  b = 0;
+    if (0 && a++ < 5 || b++ < 5) begin end
+    `checkh(a, 0);  `checkh(b, 1);
 
-      // ---- Deep nesting (3 levels &&) ----
-      a = 0;  b = 0;  c = 0;
-      if (1 && 1 && a++ < 5 && b++ < 5 && c++ < 5) begin end
-      `checkh(a, 1);  `checkh(b, 1);  `checkh(c, 1);
+    // ---- Deep nesting (3 levels &&) ----
+    a = 0;  b = 0;  c = 0;
+    if (1 && 1 && a++ < 5 && b++ < 5 && c++ < 5) begin end
+    `checkh(a, 1);  `checkh(b, 1);  `checkh(c, 1);
 
-      a = 0;  b = 0;  c = 0;
-      if (1 && 0 && a++ < 5 && b++ < 5 && c++ < 5) begin end
-      `checkh(a, 0);  `checkh(b, 0);  `checkh(c, 0);
+    a = 0;  b = 0;  c = 0;
+    if (1 && 0 && a++ < 5 && b++ < 5 && c++ < 5) begin end
+    `checkh(a, 0);  `checkh(b, 0);  `checkh(c, 0);
 
-      // ---- LHS reads variable that gated RHS ++/-- writes (single-eval) ----
-      a = 4;   if (a == 4 && a++ < 10) begin end  `checkh(a, 5);
-      a = 6;   if (a == 4 && a++ < 10) begin end  `checkh(a, 6);
-      a = 0;   if (a < 1  && a++ < 5)  begin end  `checkh(a, 1);
-      a = 5;   if (a > 0  && a-- > 0)  begin end  `checkh(a, 4);
-      a = 4;   if (a == 4 && ++a < 10) begin end  `checkh(a, 5);
+    // ---- LHS reads variable that gated RHS ++/-- writes (single-eval) ----
+    a = 4;  if (a == 4 && a++ < 10) begin end  `checkh(a, 5);
+    a = 6;  if (a == 4 && a++ < 10) begin end  `checkh(a, 6);
+    a = 0;  if (a < 1  && a++ < 5)  begin end  `checkh(a, 1);
+    a = 5;  if (a > 0  && a-- > 0)  begin end  `checkh(a, 4);
+    a = 4;  if (a == 4 && ++a < 10) begin end  `checkh(a, 5);
 
-      // ---- || mirror: LHS reads variable that gated RHS modifies ----
-      a = 4;   if (a != 4 || a++ < 10) begin end  `checkh(a, 5);
-      a = 6;   if (a != 4 || a++ < 10) begin end  `checkh(a, 6);
+    // ---- || mirror: LHS reads variable that gated RHS modifies ----
+    a = 4;  if (a != 4 || a++ < 10) begin end  `checkh(a, 5);
+    a = 6;  if (a != 4 || a++ < 10) begin end  `checkh(a, 6);
 
-      // ---- Nested gate: inner && with non-const LHS inside an outer gate ----
-      a = 4;   if (a == 4 && (a < 10 && a++ < 20)) begin end  `checkh(a, 5);
-      a = 20;  if (a == 20 && (a < 10 && a++ < 30)) begin end `checkh(a, 20);
-      a = 0;   if (a == 4 && (a < 10 && a++ < 20)) begin end  `checkh(a, 0);
+    // ---- Nested gate: inner && with non-const LHS inside an outer gate ----
+    a = 4;  if (a == 4 && (a < 10 && a++ < 20)) begin end  `checkh(a, 5);
+    a = 20;  if (a == 20 && (a < 10 && a++ < 30)) begin end `checkh(a, 20);
+    a = 0;  if (a == 4 && (a < 10 && a++ < 20)) begin end  `checkh(a, 0);
 
-      // ---- ++/-- in && / || inside a function (function-local temp) ----
-      `checkh(f_and(5), 6);     // 5>0 true, post-inc runs -> 6
-      `checkh(f_and(0), 0);     // 0>0 false, short-circuit -> unchanged
-      `checkh(f_or(5), 5);      // 5>0 true, short-circuit -> unchanged
-      `checkh(f_or(0), 1);      // 0>0 false, post-inc runs -> 1
-      `checkh(f_single(4), 1005); // 4==4 (once) && 4<100 -> taken=1, x=5
-      `checkh(f_single(6), 6);  // 6==4 false, short-circuit -> taken=0, x=6
+    // ---- ++/-- in && / || inside a function (function-local temp) ----
+    `checkh(f_and(5), 6);    // 5>0 true, post-inc runs -> 6
+    `checkh(f_and(0), 0);    // 0>0 false, short-circuit -> unchanged
+    `checkh(f_or(5), 5);    // 5>0 true, short-circuit -> unchanged
+    `checkh(f_or(0), 1);    // 0>0 false, post-inc runs -> 1
+    `checkh(f_single(4), 1005); // 4==4 (once) && 4<100 -> taken=1, x=5
+    `checkh(f_single(6), 6);  // 6==4 false, short-circuit -> taken=0, x=6
 
-      // ---- Impure (side-effecting) LHS must be evaluated exactly once ----
-      side = 0;  a = 0;  if (bump() > 0 && a++ < 5) begin end  `checkh(side, 1);  `checkh(a, 1);
-      side = 0;  a = 0;  if (bump() < 0 && a++ < 5) begin end  `checkh(side, 1);  `checkh(a, 0);
+    // ---- Impure (side-effecting) LHS must be evaluated exactly once ----
+    side = 0;  a = 0;  if (bump() > 0 && a++ < 5) begin end  `checkh(side, 1);  `checkh(a, 1);
+    side = 0;  a = 0;  if (bump() < 0 && a++ < 5) begin end  `checkh(side, 1);  `checkh(a, 0);
 
-      // ---- ++/-- on LHS, side-effecting function on opposite (RHS) side ----
-      side = 0;  a = 0;  if (a++ < 5 && bump() > 0) begin end  `checkh(a, 1);  `checkh(side, 1);
-      side = 0;  a = 0;  if (a++ > 5 && bump() > 0) begin end  `checkh(a, 1);  `checkh(side, 0);
-      side = 0;  a = 0;  if (a++ > 5 || bump() > 0) begin end  `checkh(a, 1);  `checkh(side, 1);
-      side = 0;  a = 0;  if (a++ < 5 || bump() > 0) begin end  `checkh(a, 1);  `checkh(side, 0);
+    // ---- ++/-- on LHS, side-effecting function on opposite (RHS) side ----
+    side = 0;  a = 0;  if (a++ < 5 && bump() > 0) begin end  `checkh(a, 1);  `checkh(side, 1);
+    side = 0;  a = 0;  if (a++ > 5 && bump() > 0) begin end  `checkh(a, 1);  `checkh(side, 0);
+    side = 0;  a = 0;  if (a++ > 5 || bump() > 0) begin end  `checkh(a, 1);  `checkh(side, 1);
+    side = 0;  a = 0;  if (a++ < 5 || bump() > 0) begin end  `checkh(a, 1);  `checkh(side, 0);
 
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule

test_regress/t/t_module_reserved_keyword.v

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module interrupt (
-    input  logic clk_i = 1,
-    input  logic rst_ni = 1
+    input logic clk_i = 1,
+    input logic rst_ni = 1
 );
 endmodule

test_regress/t/t_randomize_shift_distribution.v

@@ -70,9 +70,21 @@ module t;
     for (int b = 0; b < 15; b++) `check_le(r.fa15.m_ones[b], HI);
     for (int b = 0; b < 31; b++) `check_le(r.fa31.m_ones[b], HI);
     for (int b = 0; b < 32; b++) `check_le(r.fa32.m_ones[b], HI);
-    for (int b = 0; b < 15; b++) if (r.fa15.m_ones[b] < LO) begin $write("%%Error: fa15[%0d] ones=%0d < %0d\n", b, r.fa15.m_ones[b], LO); `stop; end
-    for (int b = 0; b < 31; b++) if (r.fa31.m_ones[b] < LO) begin $write("%%Error: fa31[%0d] ones=%0d < %0d\n", b, r.fa31.m_ones[b], LO); `stop; end
-    for (int b = 0; b < 32; b++) if (r.fa32.m_ones[b] < LO) begin $write("%%Error: fa32[%0d] ones=%0d < %0d\n", b, r.fa32.m_ones[b], LO); `stop; end
+    for (int b = 0; b < 15; b++)
+    if (r.fa15.m_ones[b] < LO) begin
+      $write("%%Error: fa15[%0d] ones=%0d < %0d\n", b, r.fa15.m_ones[b], LO);
+      `stop;
+    end
+    for (int b = 0; b < 31; b++)
+    if (r.fa31.m_ones[b] < LO) begin
+      $write("%%Error: fa31[%0d] ones=%0d < %0d\n", b, r.fa31.m_ones[b], LO);
+      `stop;
+    end
+    for (int b = 0; b < 32; b++)
+    if (r.fa32.m_ones[b] < LO) begin
+      $write("%%Error: fa32[%0d] ones=%0d < %0d\n", b, r.fa32.m_ones[b], LO);
+      `stop;
+    end
     // High bits beyond m_size must remain 0.
     for (int b = 1; b < 64; b++) `checkd(r.fa1.m_ones[b], 0);
     for (int b = 15; b < 64; b++) `checkd(r.fa15.m_ones[b], 0);