Fix insertion of expression coverage statement (#7832)

Signed-off-by: Ryszard Rozak <rrozak@antmicro.com>

src/V3Coverage.cpp

@@ -375,6 +375,8 @@ class CoverageVisitor final : public VNVisitor {
             } else {
                 itemp->addElsesp(stmtp);
             }
+        } else if (AstBegin* const itemp = VN_CAST(nodep, Begin)) {
+            itemp->addStmtsp(stmtp);
         } else {
             nodep->v3fatalSrc("Bad node type");
         }
@@ -776,6 +778,8 @@ class CoverageVisitor final : public VNVisitor {
         // covers the code in that line.)
         VL_RESTORER(m_beginHier);
         VL_RESTORER(m_inToggleOff);
+        VL_RESTORER(m_exprStmtsp);
+        m_exprStmtsp = nodep;
         m_inToggleOff = true;
         if (nodep->name() != "") {
             m_beginHier = m_beginHier + (m_beginHier != "" ? "__DOT__" : "") + nodep->name();

test_regress/t/t_cover_expr_fork.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2025 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--coverage-expr --binary'])
+
+test.execute()
+
+test.passes()

test_regress/t/t_cover_expr_fork.v

@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  int cnt = 0;
+  task automatic myTask;
+    fork
+      begin
+        bit x;
+        if (!x) begin
+          cnt++;
+        end
+      end
+    join_none
+  endtask
+
+  initial begin
+    myTask();
+    #1;
+    if (cnt != 1) $stop;
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule