Fixes #7498.
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2875ec8655
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@ -88,6 +88,7 @@ Gökçe Aydos
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Han Qi
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Harald Heckmann
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Hennadii Chernyshchyk
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hjsanjana
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Howard Su
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Huang Rui
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Huanghuang Zhou
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@ -2824,6 +2824,11 @@ class CaptureVisitor final : public VNVisitor {
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&& varRefp->varp()->lifetime().isStatic())
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return CaptureMode::CAP_NO;
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if (callerIsClass && varIsFieldOfCaller) return CaptureMode::CAP_THIS;
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// Static member of a different class: V3Width replaces AstMemberSel with a bare
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// AstVarRef (classOrPackagep set). Capture current value as a function argument.
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if (callerIsClass && varClassp && !varIsFieldOfCaller
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&& varRefp->varp()->lifetime().isStatic())
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return CaptureMode::CAP_VALUE;
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UASSERT_OBJ(!callerIsClass, varRefp, "Invalid reference?");
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return CaptureMode::CAP_VALUE;
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}
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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if not test.have_solver:
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test.skip("No constraint solver installed")
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,80 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// Regression test for GitHub issue #7498:
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// std::randomize() constraint referencing a static class member of a
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// *different* class (accessed via a foreach loop) caused an internal error
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// in V3Randomize ("Invalid reference?").
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package tlogy_m_pkg;
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class v_cfg;
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static int num_of_ds = 0;
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endclass
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class tlogy_m;
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v_cfg v[$];
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endclass
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endpackage
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package s_pkg;
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import tlogy_m_pkg::*;
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class s_cfg;
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tlogy_m t_m;
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bit t_mode;
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int a_d_idx;
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function void setup_h_iw_cfg();
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if (t_mode) begin
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foreach (t_m.v[i]) begin
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if (std::randomize(a_d_idx) with {
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if (t_m.v[i].num_of_ds > 1) {
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a_d_idx inside {[0:(t_m.v[i].num_of_ds - 1)]};
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a_d_idx != 0;
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}
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} == 0)
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$stop;
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end
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end
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endfunction
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endclass
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endpackage
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module t;
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import tlogy_m_pkg::*;
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import s_pkg::*;
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initial begin
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automatic s_cfg cfg = new;
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automatic tlogy_m tm = new;
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automatic v_cfg vc0 = new;
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automatic v_cfg vc1 = new;
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// Set up: push two entries in the queue and set num_of_ds = 3
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// so the constraint branch (num_of_ds > 1) is exercised.
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tm.v.push_back(vc0);
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tm.v.push_back(vc1);
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v_cfg::num_of_ds = 3;
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cfg.t_m = tm;
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cfg.t_mode = 1'b1;
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repeat (20) begin
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cfg.setup_h_iw_cfg();
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// When num_of_ds = 3 the constraint is:
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// a_d_idx inside {[0:2]} && a_d_idx != 0
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// so a_d_idx must be 1 or 2.
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if (cfg.a_d_idx < 1 || cfg.a_d_idx > 2) $stop;
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end
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// Also verify that the "no constraint" branch (num_of_ds <= 1)
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// compiles and runs without crashing.
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v_cfg::num_of_ds = 0;
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cfg.setup_h_iw_cfg();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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