Tests: Add t_param_type, bug480. Merge from JERAS/test_sv.

test_regress/t/t_param_type.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug480");
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_param_type.v

@@ -0,0 +1,67 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Iztok Jeras.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   // counters
+   int cnt;
+   int cnt_bit ;
+   int cnt_byte;
+   int cnt_int ;
+   int cnt_ar1d;
+   int cnt_ar2d;
+
+   // sizes
+   int siz_bit ;
+   int siz_byte;
+   int siz_int ;
+   int siz_ar1d;
+   int siz_ar2d;
+
+   // add all counters
+   assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d;
+
+   // finish report
+   always @ (posedge clk)
+   if (cnt == 5) begin
+      if (siz_bit  !=  1)  $stop();
+      if (siz_byte !=  8)  $stop();
+      if (siz_int  != 32)  $stop();
+      if (siz_ar1d != 24)  $stop();
+      if (siz_ar2d != 16)  $stop();
+   end else if (cnt > 5) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   // instances with various types
+   mod_typ #(.TYP (bit           )) mod_bit  (clk, cnt_bit [ 1-1:0], siz_bit );
+   mod_typ #(.TYP (byte          )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte);
+   mod_typ #(.TYP (int           )) mod_int  (clk, cnt_int [32-1:0], siz_int );
+   mod_typ #(.TYP (bit [23:0]    )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d);
+   mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d);
+
+endmodule : t
+
+
+module mod_typ #(
+   parameter type TYP = byte
+)(
+   input  logic clk,
+   output TYP   cnt = 0,
+   output int   siz
+);
+
+   always @ (posedge clk)
+     cnt <= cnt + 1;
+
+   assign siz = $bits (cnt);
+
+endmodule