Support parsing min:typ:max parameters
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@ -2940,7 +2940,7 @@ delay_control<delayp>: //== IEEE: delay_control
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| '#' '(' minTypMax ',' minTypMax ')'
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| '#' '(' minTypMax ',' minTypMax ')'
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{ $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($3); DEL($5); }
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{ $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($3); DEL($5); }
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| '#' '(' minTypMax ',' minTypMax ',' minTypMax ')'
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| '#' '(' minTypMax ',' minTypMax ',' minTypMax ')'
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{ $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($3); DEL($5); DEL($7); }
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{ $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($5); DEL($3); DEL($7); }
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;
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;
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delay_value<nodeExprp>: // ==IEEE:delay_value
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delay_value<nodeExprp>: // ==IEEE:delay_value
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@ -4785,7 +4785,7 @@ expr<nodeExprp>: // IEEE: part of expression/constant_expression/
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// // IEEE: '(' mintypmax_expression ')'
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// // IEEE: '(' mintypmax_expression ')'
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| ~noPar__IGNORE~'(' expr ')' { $$ = $2; }
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| ~noPar__IGNORE~'(' expr ')' { $$ = $2; }
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| ~noPar__IGNORE~'(' expr ':' expr ':' expr ')'
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| ~noPar__IGNORE~'(' expr ':' expr ':' expr ')'
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{ $$ = $2; BBUNSUP($1, "Unsupported: min typ max expressions"); }
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{ $$ = $4; MINTYPMAXDLYUNSUP($4); DEL($2); DEL($6); }
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// // PSL rule
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// // PSL rule
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| '_' '(' expr ')' { $$ = $3; } // Arbitrary Verilog inside PSL
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| '_' '(' expr ')' { $$ = $3; } // Arbitrary Verilog inside PSL
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//
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//
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@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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@ -0,0 +1,17 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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parameter MTM = (1:2:3);
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initial begin
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if (MTM != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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