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@ -200,6 +200,7 @@ Nathan Graybeal
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Nathan Kohagen
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Nathan Myers
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Nick Brereton
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Nikolai Kumar
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Nikolay Puzanov
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Nolan Poe
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Oleh Maksymenko
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@ -275,9 +275,7 @@ public:
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int widthAlignBytes() const override;
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// (Slow) recurses - Width in bytes rounding up 1,2,4,8,12,...
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int widthTotalBytes() const override;
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bool similarDTypeNode(const AstNodeDType* samep) const override {
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return this == samep; // We don't compare members, require exact equivalence
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}
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bool similarDTypeNode(const AstNodeDType* samep) const override;
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string name() const override VL_MT_STABLE { return m_name; }
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void name(const string& flag) override { m_name = flag; }
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bool packed() const VL_MT_SAFE { return m_packed; }
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@ -2003,6 +2003,21 @@ bool AstClassRefDType::similarDTypeNode(const AstNodeDType* samep) const {
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}
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return !lp && !rp;
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}
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bool AstNodeUOrStructDType::similarDTypeNode(const AstNodeDType* samep) const {
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const AstNodeUOrStructDType* const sp = VN_DBG_AS(samep, NodeUOrStructDType);
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if (m_packed != sp->m_packed) return false;
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if (fileline()->tokenNum() != sp->fileline()->tokenNum()) return false;
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const AstMemberDType* lp = membersp();
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const AstMemberDType* rp = sp->membersp();
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while (lp && rp) {
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if (lp->name() != rp->name()) return false;
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if (lp->width() != rp->width()) return false;
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if (!lp->subDTypep()->similarDType(rp->subDTypep())) return false;
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lp = VN_CAST(lp->nextp(), MemberDType);
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rp = VN_CAST(rp->nextp(), MemberDType);
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}
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return !lp && !rp;
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}
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void AstNodeCoverOrAssert::dump(std::ostream& str) const {
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this->AstNodeStmt::dump(str);
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str << " ["s + this->userType().ascii() + "]";
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--binary"])
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test.execute()
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test.passes()
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@ -0,0 +1,51 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Nikolai Kumar
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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class C #(parameter P = 0);
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typedef struct packed {
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bit [7:0] x;
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} my_t;
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mailbox #(my_t) mb = new();
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task run(output bit [7:0] got);
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my_t v;
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mb.get(v);
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got = v.x;
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endtask
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endclass
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endpackage
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module top;
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import pkg::*;
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initial begin
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C #(0) c0;
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C #(1) c1;
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C#(0)::my_t s0;
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C#(1)::my_t s1;
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bit [7:0] got0;
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bit [7:0] got1;
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c0 = new();
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c1 = new();
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s0.x = 8'hA5;
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s1.x = 8'h5A;
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c0.mb.put(s0);
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c1.mb.put(s1);
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c0.run(got0);
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c1.run(got1);
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if(got0 !== 8'hA5) $stop;
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if(got0 !== 8'hA5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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