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Support 1800-2023 keywords.

This commit is contained in:
Wilson Snyder 2024-03-02 09:01:37 -05:00
parent a378dbd9b2
commit 91dd3c5fac
21 changed files with 121 additions and 92 deletions
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5
Changes
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@ -11,6 +11,11 @@ contributors that suggested a given feature are shown in []. Thanks!
Verilator 5.023 devel Verilator 5.023 devel
========================== ==========================
**Major:**
* Support 1800-2023 keywords.
**Minor:** **Minor:**
* Add warning on 'TOP'-named modules (#4935). [Yanglin Xun] * Add warning on 'TOP'-named modules (#4935). [Yanglin Xun]

3
bin/verilator
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@ -308,6 +308,7 @@ detailed descriptions of these arguments.
+1800-2009ext+<ext> Use SystemVerilog 2009 with file extension <ext> +1800-2009ext+<ext> Use SystemVerilog 2009 with file extension <ext>
+1800-2012ext+<ext> Use SystemVerilog 2012 with file extension <ext> +1800-2012ext+<ext> Use SystemVerilog 2012 with file extension <ext>
+1800-2017ext+<ext> Use SystemVerilog 2017 with file extension <ext> +1800-2017ext+<ext> Use SystemVerilog 2017 with file extension <ext>
+1800-2023ext+<ext> Use SystemVerilog 2023 with file extension <ext>
--assert Enable all assertions --assert Enable all assertions
--assert-case Enable unique/unique0/priority case related checks --assert-case Enable unique/unique0/priority case related checks
--autoflush Flush streams after all $displays --autoflush Flush streams after all $displays
@ -437,7 +438,7 @@ detailed descriptions of these arguments.
--no-stop-fail Do not call $stop when assertion fails --no-stop-fail Do not call $stop when assertion fails
--structs-packed Convert all unpacked structures to packed structures --structs-packed Convert all unpacked structures to packed structures
-sv Enable SystemVerilog parsing -sv Enable SystemVerilog parsing
+systemverilogext+<ext> Synonym for +1800-2017ext+<ext> +systemverilogext+<ext> Synonym for +1800-2023ext+<ext>
--threads <threads> Enable multithreading --threads <threads> Enable multithreading
--threads-dpi <mode> Enable multithreaded DPI --threads-dpi <mode> Enable multithreaded DPI
--threads-max-mtasks <mtasks> Tune maximum mtask partitioning --threads-max-mtasks <mtasks> Tune maximum mtask partitioning

10
docs/guide/exe_verilator.rst
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@ -51,6 +51,8 @@ Summary:
.. option:: +1800-2017ext+<ext> .. option:: +1800-2017ext+<ext>
.. option:: +1800-2023ext+<ext>
Specifies the language standard to be used with a specific filename Specifies the language standard to be used with a specific filename
extension, <ext>. extension, <ext>.
@ -349,7 +351,7 @@ Summary:
Select the language used by default when first processing each Select the language used by default when first processing each
Verilog file. The language value must be "VAMS", "1364-1995", Verilog file. The language value must be "VAMS", "1364-1995",
"1364-2001", "1364-2001-noconfig", "1364-2005", "1800-2005", "1364-2001", "1364-2001-noconfig", "1364-2005", "1800-2005",
"1800-2009", "1800-2012", "1800-2017", or "1800+VAMS". "1800-2009", "1800-2012", "1800-2017", "1800-2023", or "1800+VAMS".
Any language associated with a particular file extension (see the Any language associated with a particular file extension (see the
various +<lang>*\ ext+ options) will be used in preference to the various +<lang>*\ ext+ options) will be used in preference to the
@ -362,7 +364,7 @@ Summary:
``+<lang>ext+`` options should be used. ``+<lang>ext+`` options should be used.
If no language is specified, either by this option or ``+<lang>ext+`` If no language is specified, either by this option or ``+<lang>ext+``
options, then the latest SystemVerilog language (IEEE 1800-2017) is options, then the latest SystemVerilog language (IEEE 1800-2023) is
used. used.
.. option:: +define+<var>=<value> .. option:: +define+<var>=<value>
@ -1299,12 +1301,12 @@ Summary:
.. option:: -sv .. option:: -sv
Specifies SystemVerilog language features should be enabled; equivalent Specifies SystemVerilog language features should be enabled; equivalent
to :vlopt:`--language 1800-2017 <--language>`. This option is selected to :vlopt:`--language 1800-2023 <--language>`. This option is selected
by default; it exists for compatibility with other simulators. by default; it exists for compatibility with other simulators.
.. option:: +systemverilogext+<ext> .. option:: +systemverilogext+<ext>
A synonym for :vlopt:`+1800-2017ext+\<ext\>`. A synonym for :vlopt:`+1800-2023ext+\<ext\>`.
.. option:: --threads <threads> .. option:: --threads <threads>

5
docs/guide/extensions.rst
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@ -36,8 +36,7 @@ or "`ifdef`"'s may break other tools.
.. option:: """ [string] """ .. option:: """ [string] """
A triple-quoted block specifies a string that may include newlines and A triple-quoted block specifies a string that may include newlines and
single quotes. This extension is experimental and may be removed single quotes. This extension was standardized in IEEE 1800-2023.
without deprecation.
.. option:: $c([string], ...); .. option:: $c([string], ...);
@ -619,4 +618,4 @@ or "`ifdef`"'s may break other tools.
symbols. Also, the data represents the C++ stack; the SystemVerilog symbols. Also, the data represents the C++ stack; the SystemVerilog
functions/tasks involved may be renamed and/or inlined before becoming functions/tasks involved may be renamed and/or inlined before becoming
the C++ functions that may be visible in the stack trace. This the C++ functions that may be visible in the stack trace. This
extension is experimental and may be removed without deprecation. extension was standardized in IEEE 1800-2023.

7
docs/guide/languages.rst
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@ -62,6 +62,13 @@ Verilator supports the 2017 "for" loop constructs and several cleanups IEEE
made in 1800-2017. made in 1800-2017.
SystemVerilog 2023 (IEEE 1800-2023) Support
-------------------------------------------
Verilator supports some of the 2023 improvements, including triple-quoted
string blocks that may include newlines and single quotes.
Verilog AMS Support Verilog AMS Support
------------------- -------------------

6
docs/guide/overview.rst
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@ -50,6 +50,6 @@ The best place to get started is to try the :ref:`Examples`.
.. [#] SystemVerilog is defined by the `Institute of Electrical and .. [#] SystemVerilog is defined by the `Institute of Electrical and
Electronics Engineers (IEEE) Standard for SystemVerilog - Unified Electronics Engineers (IEEE) Standard for SystemVerilog - Unified
Hardware Design, Specification, and Verification Language`, Standard Hardware Design, Specification, and Verification Language`, Standard
1800, released in 2005, 2009, 2012, and 2017. The Verilator 1800, released in 2005, 2009, 2012, 2017, and 2023. The Verilator
documentation uses the shorthand e.g., "IEEE 1800-2017", to refer to documentation uses the shorthand e.g., "IEEE 1800-2023", to refer to
the, e.g., 2017 version of this standard. the, e.g., 2023 version of this standard.

13
src/V3LangCode.h
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@ -39,18 +39,21 @@ public:
L1800_2009, L1800_2009,
L1800_2012, L1800_2012,
L1800_2017, L1800_2017,
L1800_2023,
// ***Add new elements below also*** // ***Add new elements below also***
_ENUM_END _ENUM_END
}; };
const char* ascii() const { const char* ascii() const {
const char* const names[] = {// These must match the `begin_keywords values. const char* const names[]
" ERROR", "1364-1995", "1364-2001", "1364-2005", = {// These must match the `begin_keywords values
"1800-2005", "1800-2009", "1800-2012", "1800-2017"}; " ERROR", "1364-1995", "1364-2001", "1364-2005", "1800-2005",
"1800-2009", "1800-2012", "1800-2017", "1800-2023"};
return names[m_e]; return names[m_e];
} }
static V3LangCode mostRecent() VL_MT_SAFE { return V3LangCode{L1800_2017}; } static V3LangCode mostRecent() VL_MT_SAFE { return V3LangCode{L1800_2023}; }
bool systemVerilog() const { bool systemVerilog() const {
return m_e == L1800_2005 || m_e == L1800_2009 || m_e == L1800_2012 || m_e == L1800_2017; return m_e == L1800_2005 || m_e == L1800_2009 || m_e == L1800_2012 || m_e == L1800_2017
|| m_e == L1800_2023;
} }
bool legal() const { return m_e != L_ERROR; } bool legal() const { return m_e != L_ERROR; }
// //

4
src/V3Options.cpp
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@ -1102,6 +1102,8 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
[this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2012); }); [this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2012); });
DECL_OPTION("+1800-2017ext+", CbPartialMatch, DECL_OPTION("+1800-2017ext+", CbPartialMatch,
[this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2017); }); [this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2017); });
DECL_OPTION("+1800-2023ext+", CbPartialMatch,
[this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2023); });
// Minus options // Minus options
DECL_OPTION("-assert", OnOff, &m_assert); DECL_OPTION("-assert", OnOff, &m_assert);
@ -1446,7 +1448,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
DECL_OPTION("-std", OnOff, &m_std); DECL_OPTION("-std", OnOff, &m_std);
DECL_OPTION("-stop-fail", OnOff, &m_stopFail); DECL_OPTION("-stop-fail", OnOff, &m_stopFail);
DECL_OPTION("-structs-packed", OnOff, &m_structsPacked); DECL_OPTION("-structs-packed", OnOff, &m_structsPacked);
DECL_OPTION("-sv", CbCall, [this]() { m_defaultLanguage = V3LangCode::L1800_2017; }); DECL_OPTION("-sv", CbCall, [this]() { m_defaultLanguage = V3LangCode::L1800_2023; });
DECL_OPTION("-threads-coarsen", OnOff, &m_threadsCoarsen).undocumented(); // Debug DECL_OPTION("-threads-coarsen", OnOff, &m_threadsCoarsen).undocumented(); // Debug
DECL_OPTION("-no-threads", CbCall, [this, fl]() { DECL_OPTION("-no-threads", CbCall, [this, fl]() {

41
src/verilog.l
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@ -27,7 +27,7 @@
#include "V3ParseBison.h" // Generated by bison #include "V3ParseBison.h" // Generated by bison
#include "V3ParseImp.h" // Defines YYTYPE; before including bison header #include "V3ParseImp.h" // Defines YYTYPE; before including bison header
#define STATE_VERILOG_RECENT S17 // State name for most recent Verilog Version #define STATE_VERILOG_RECENT S23 // State name for most recent Verilog Version
#define PARSEP V3ParseImp::parsep() #define PARSEP V3ParseImp::parsep()
@ -78,7 +78,7 @@ static double lexParseDouble(FileLine* fl, const char* textp, size_t length) {
%a 15000 %a 15000
%o 25000 %o 25000
%s V95 V01NC V01C V05 S05 S09 S12 S17 %s V95 V01NC V01C V05 S05 S09 S12 S17 S23
%s ATTRMODE QQQ STRING TABLE %s ATTRMODE QQQ STRING TABLE
%s VA5 SAX VLT %s VA5 SAX VLT
%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
@ -159,7 +159,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/ /************************************************************************/
/* Verilog 1995 */ /* Verilog 1995 */
<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX>{
{ws} { FL_FWD; FL_BRK; } /* otherwise ignore white-space */ {ws} { FL_FWD; FL_BRK; } /* otherwise ignore white-space */
{crnl} { FL_FWD; FL_BRK; } /* Count line numbers */ {crnl} { FL_FWD; FL_BRK; } /* Count line numbers */
/* Extensions to Verilog set, some specified by PSL */ /* Extensions to Verilog set, some specified by PSL */
@ -410,7 +410,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* Verilog 2001 */ /* Verilog 2001 */
<V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{ <V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX>{
/* System Tasks */ /* System Tasks */
"$signed" { FL; return yD_SIGNED; } "$signed" { FL; return yD_SIGNED; }
"$unsigned" { FL; return yD_UNSIGNED; } "$unsigned" { FL; return yD_UNSIGNED; }
@ -430,7 +430,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* Verilog 2001 Config */ /* Verilog 2001 Config */
<V01C,V05,VA5,S05,S09,S12,S17,SAX>{ <V01C,V05,VA5,S05,S09,S12,S17,S23,SAX>{
/* Generic unsupported keywords */ /* Generic unsupported keywords */
"cell" { ERROR_RSVD_WORD("Verilog 2001-config"); } "cell" { ERROR_RSVD_WORD("Verilog 2001-config"); }
"config" { ERROR_RSVD_WORD("Verilog 2001-config"); } "config" { ERROR_RSVD_WORD("Verilog 2001-config"); }
@ -447,7 +447,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* Verilog 2005 */ /* Verilog 2005 */
<V05,S05,S09,S12,S17,SAX>{ <V05,S05,S09,S12,S17,S23,SAX>{
/* System Tasks */ /* System Tasks */
"$clog2" { FL; return yD_CLOG2; } "$clog2" { FL; return yD_CLOG2; }
/* Keywords */ /* Keywords */
@ -455,7 +455,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* System Verilog 2005 */ /* System Verilog 2005 */
<S05,S09,S12,S17,SAX>{ <S05,S09,S12,S17,S23,SAX>{
/* System Tasks */ /* System Tasks */
"$bits" { FL; return yD_BITS; } "$bits" { FL; return yD_BITS; }
"$changed" { FL; return yD_CHANGED; } "$changed" { FL; return yD_CHANGED; }
@ -590,7 +590,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* SystemVerilog 2009 */ /* SystemVerilog 2009 */
<S09,S12,S17,SAX>{ <S09,S12,S17,S23,SAX>{
/* Keywords */ /* Keywords */
"accept_on" { FL; return yACCEPT_ON; } "accept_on" { FL; return yACCEPT_ON; }
"checker" { FL; return yCHECKER; } "checker" { FL; return yCHECKER; }
@ -617,7 +617,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* System Verilog 2012 */ /* System Verilog 2012 */
<S12,S17,SAX>{ <S12,S17,S23,SAX>{
/* Keywords */ /* Keywords */
"implements" { FL; return yIMPLEMENTS; } "implements" { FL; return yIMPLEMENTS; }
"interconnect" { FL; return yINTERCONNECT; } "interconnect" { FL; return yINTERCONNECT; }
@ -629,7 +629,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* No new keywords */ /* No new keywords */
/* Default PLI rule */ /* Default PLI rule */
<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX>{
"$"[a-zA-Z0-9_$]+ { const string str (yytext, yyleng); "$"[a-zA-Z0-9_$]+ { const string str (yytext, yyleng);
yylval.strp = PARSEP->newString(AstNode::encodeName(str)); yylval.strp = PARSEP->newString(AstNode::encodeName(str));
FL; return yaD_PLI; FL; return yaD_PLI;
@ -734,7 +734,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Meta comments */ /* Meta comments */
/* Converted from //{cmt}verilator ...{cmt} by preprocessor */ /* Converted from //{cmt}verilator ...{cmt} by preprocessor */
<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX>{
"/*verilator"{ws}*"*/" { FL_FWD; FL_BRK; } /* Ignore empty comments, may be `endif // verilator */ "/*verilator"{ws}*"*/" { FL_FWD; FL_BRK; } /* Ignore empty comments, may be `endif // verilator */
"/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; } "/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; }
"/*verilator clocker*/" { FL; return yVL_CLOCKER; } "/*verilator clocker*/" { FL; return yVL_CLOCKER; }
@ -786,7 +786,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/ /************************************************************************/
/* Single character operator thingies */ /* Single character operator thingies */
<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX>{
"{" { FL; return yytext[0]; } "{" { FL; return yytext[0]; }
"}" { FL; return yytext[0]; } "}" { FL; return yytext[0]; }
"!" { FL; return yytext[0]; } "!" { FL; return yytext[0]; }
@ -820,7 +820,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Operators and multi-character symbols */ /* Operators and multi-character symbols */
/* Verilog 1995 Operators */ /* Verilog 1995 Operators */
<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX>{
"&&" { FL; return yP_ANDAND; } "&&" { FL; return yP_ANDAND; }
"||" { FL; return yP_OROR; } "||" { FL; return yP_OROR; }
"<=" { FL; return yP_LTE; } "<=" { FL; return yP_LTE; }
@ -842,7 +842,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* Verilog 2001 Operators */ /* Verilog 2001 Operators */
<V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{ <V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX>{
"<<<" { FL; return yP_SLEFT; } "<<<" { FL; return yP_SLEFT; }
">>>" { FL; return yP_SSRIGHT; } ">>>" { FL; return yP_SSRIGHT; }
"**" { FL; return yP_POW; } "**" { FL; return yP_POW; }
@ -855,7 +855,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* SystemVerilog Operators */ /* SystemVerilog Operators */
<S05,S09,S12,S17,SAX>{ <S05,S09,S12,S17,S23,SAX>{
"'" { FL; return yP_TICK; } "'" { FL; return yP_TICK; }
"'{" { FL; return yP_TICKBRA; } "'{" { FL; return yP_TICKBRA; }
"==?" { FL; return yP_WILDEQUAL; } "==?" { FL; return yP_WILDEQUAL; }
@ -892,12 +892,12 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
} }
/* SystemVerilog 2009 Operators */ /* SystemVerilog 2009 Operators */
<S09,S12,S17,SAX,VLT>{ <S09,S12,S17,S23,SAX,VLT>{
"<->" { FL; return yP_LTMINUSGT; } "<->" { FL; return yP_LTMINUSGT; }
} }
/* Identifiers and numbers */ /* Identifiers and numbers */
<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX,VLT>{
{escid} { FL; yylval.strp = PARSEP->newString {escid} { FL; yylval.strp = PARSEP->newString
(AstNode::encodeName(std::string{yytext+1})); // +1 to skip the backslash (AstNode::encodeName(std::string{yytext+1})); // +1 to skip the backslash
return yaID__LEX; return yaID__LEX;
@ -991,7 +991,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/ /************************************************************************/
/* Attributes */ /* Attributes */
/* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */ /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX>{
"(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */ "(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */
} }
@ -1011,7 +1011,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Common for all SYSC header states */ /* Common for all SYSC header states */
/* OPTIMIZE: we return one per line, make it one for the entire block */ /* OPTIMIZE: we return one per line, make it one for the entire block */
/* If add to this list also add to V3LanguageWords.h */ /* If add to this list also add to V3LanguageWords.h */
<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR>{
"`accelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility "`accelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
"`autoexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility "`autoexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
"`celldefine" { FL_FWD; PARSEP->lexFileline()->celldefineOn(true); FL_BRK; } "`celldefine" { FL_FWD; PARSEP->lexFileline()->celldefineOn(true); FL_BRK; }
@ -1067,6 +1067,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"`begin_keywords"[ \t]*\"1800-2009\" { FL_FWD; yy_push_state(S09); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"1800-2009\" { FL_FWD; yy_push_state(S09); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
"`begin_keywords"[ \t]*\"1800-2012\" { FL_FWD; yy_push_state(S12); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"1800-2012\" { FL_FWD; yy_push_state(S12); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
"`begin_keywords"[ \t]*\"1800-2017\" { FL_FWD; yy_push_state(S17); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"1800-2017\" { FL_FWD; yy_push_state(S17); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
"`begin_keywords"[ \t]*\"1800-2023\" { FL_FWD; yy_push_state(S23); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
"`begin_keywords"[ \t]*\"1800[+]VAMS\" { FL_FWD; yy_push_state(SAX); PARSEP->lexPushKeywords(YY_START); FL_BRK; } /*Latest SV*/ "`begin_keywords"[ \t]*\"1800[+]VAMS\" { FL_FWD; yy_push_state(SAX); PARSEP->lexPushKeywords(YY_START); FL_BRK; } /*Latest SV*/
"`end_keywords" { FL; "`end_keywords" { FL;
if (!PARSEP->lexPopKeywords()) { if (!PARSEP->lexPopKeywords()) {
@ -1108,7 +1109,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/************************************************************************/ /************************************************************************/
/* Default rules - leave last */ /* Default rules - leave last */
<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT>{ <V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX,VLT>{
"`"[a-zA-Z_0-9]+ { FL; V3ParseImp::lexErrorPreprocDirective(yylval.fl, yytext); FL_BRK; } "`"[a-zA-Z_0-9]+ { FL; V3ParseImp::lexErrorPreprocDirective(yylval.fl, yytext); FL_BRK; }
"//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */ "//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */
. { FL; return yytext[0]; } /* return single char ops. */ . { FL; return yytext[0]; } /* return single char ops. */

10
test_regress/t/t_constraint_xml.out
View File

@ -2,13 +2,13 @@
<!-- DESCRIPTION: Verilator output: XML representation of netlist --> <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml> <verilator_xml>
<files> <files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/> <file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/> <file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2017"/> <file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_constraint_xml.v" language="1800-2017"/> <file id="d" filename="t/t_constraint_xml.v" language="1800-2023"/>
</files> </files>
<module_files> <module_files>
<file id="d" filename="t/t_constraint_xml.v" language="1800-2017"/> <file id="d" filename="t/t_constraint_xml.v" language="1800-2023"/>
</module_files> </module_files>
<cells> <cells>
<cell loc="d,53,8,53,9" name="t" submodname="t" hier="t"/> <cell loc="d,53,8,53,9" name="t" submodname="t" hier="t"/>

9
test_regress/t/t_preproc_kwd.v
View File

@ -18,6 +18,7 @@ module t (/*AUTOARG*/
s09 s09 (); s09 s09 ();
s12 s12 (); s12 s12 ();
s17 s17 (); s17 s17 ();
s23 s23 ();
a23 a23 (); a23 a23 ();
@ -83,6 +84,14 @@ module s17;
endmodule endmodule
`end_keywords `end_keywords
`begin_keywords "1800-2023"
module s23;
final begin
$write("*-* All Finished *-*\n");
end
endmodule
`end_keywords
`begin_keywords "VAMS-2.3" `begin_keywords "VAMS-2.3"
module a23; module a23;
real foo; initial foo = sqrt(2.0); real foo; initial foo = sqrt(2.0);

10
test_regress/t/t_var_port_xml.out
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@ -2,13 +2,13 @@
<!-- DESCRIPTION: Verilator output: XML representation of netlist --> <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml> <verilator_xml>
<files> <files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/> <file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/> <file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2017"/> <file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_var_port_xml.v" language="1800-2017"/> <file id="d" filename="t/t_var_port_xml.v" language="1800-2023"/>
</files> </files>
<module_files> <module_files>
<file id="d" filename="t/t_var_port_xml.v" language="1800-2017"/> <file id="d" filename="t/t_var_port_xml.v" language="1800-2023"/>
</module_files> </module_files>
<cells> <cells>
<cell loc="d,18,8,18,11" name="mh2" submodname="mh2" hier="mh2"/> <cell loc="d,18,8,18,11" name="mh2" submodname="mh2" hier="mh2"/>

10
test_regress/t/t_xml_begin_hier.out
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@ -2,13 +2,13 @@
<!-- DESCRIPTION: Verilator output: XML representation of netlist --> <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml> <verilator_xml>
<files> <files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/> <file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/> <file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2017"/> <file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_begin_hier.v" language="1800-2017"/> <file id="d" filename="t/t_xml_begin_hier.v" language="1800-2023"/>
</files> </files>
<module_files> <module_files>
<file id="d" filename="t/t_xml_begin_hier.v" language="1800-2017"/> <file id="d" filename="t/t_xml_begin_hier.v" language="1800-2023"/>
</module_files> </module_files>
<cells> <cells>
<cell loc="d,22,8,22,12" name="test" submodname="test" hier="test"> <cell loc="d,22,8,22,12" name="test" submodname="test" hier="test">

10
test_regress/t/t_xml_debugcheck.out
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@ -2,13 +2,13 @@
<!-- DESCRIPTION: Verilator output: XML representation of netlist --> <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml> <verilator_xml>
<files> <files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/> <file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/> <file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2017"/> <file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_enum_type_methods.v" language="1800-2017"/> <file id="d" filename="t/t_enum_type_methods.v" language="1800-2023"/>
</files> </files>
<module_files> <module_files>
<file id="d" filename="t/t_enum_type_methods.v" language="1800-2017"/> <file id="d" filename="t/t_enum_type_methods.v" language="1800-2023"/>
</module_files> </module_files>
<cells> <cells>
<cell loc="d,11,8,11,9" name="$root" submodname="$root" hier="$root"> <cell loc="d,11,8,11,9" name="$root" submodname="$root" hier="$root">

10
test_regress/t/t_xml_first.out
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@ -2,13 +2,13 @@
<!-- DESCRIPTION: Verilator output: XML representation of netlist --> <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml> <verilator_xml>
<files> <files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/> <file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/> <file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2017"/> <file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_first.v" language="1800-2017"/> <file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
</files> </files>
<module_files> <module_files>
<file id="d" filename="t/t_xml_first.v" language="1800-2017"/> <file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
</module_files> </module_files>
<cells> <cells>
<cell loc="d,7,8,7,9" name="t" submodname="t" hier="t"> <cell loc="d,7,8,7,9" name="t" submodname="t" hier="t">

10
test_regress/t/t_xml_flat.out
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@ -2,13 +2,13 @@
<!-- DESCRIPTION: Verilator output: XML representation of netlist --> <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml> <verilator_xml>
<files> <files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/> <file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/> <file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2017"/> <file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_first.v" language="1800-2017"/> <file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
</files> </files>
<module_files> <module_files>
<file id="d" filename="t/t_xml_first.v" language="1800-2017"/> <file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
</module_files> </module_files>
<cells> <cells>
<cell loc="d,7,8,7,9" name="$root" submodname="$root" hier="$root"/> <cell loc="d,7,8,7,9" name="$root" submodname="$root" hier="$root"/>

10
test_regress/t/t_xml_flat_no_inline_mod.out
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@ -2,13 +2,13 @@
<!-- DESCRIPTION: Verilator output: XML representation of netlist --> <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml> <verilator_xml>
<files> <files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/> <file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/> <file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2017"/> <file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_flat_no_inline_mod.v" language="1800-2017"/> <file id="d" filename="t/t_xml_flat_no_inline_mod.v" language="1800-2023"/>
</files> </files>
<module_files> <module_files>
<file id="d" filename="t/t_xml_flat_no_inline_mod.v" language="1800-2017"/> <file id="d" filename="t/t_xml_flat_no_inline_mod.v" language="1800-2023"/>
</module_files> </module_files>
<cells> <cells>
<cell loc="d,11,8,11,11" name="$root" submodname="$root" hier="$root"/> <cell loc="d,11,8,11,11" name="$root" submodname="$root" hier="$root"/>

10
test_regress/t/t_xml_flat_pub_mod.out
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@ -2,13 +2,13 @@
<!-- DESCRIPTION: Verilator output: XML representation of netlist --> <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml> <verilator_xml>
<files> <files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/> <file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/> <file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2017"/> <file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_flat_pub_mod.v" language="1800-2017"/> <file id="d" filename="t/t_xml_flat_pub_mod.v" language="1800-2023"/>
</files> </files>
<module_files> <module_files>
<file id="d" filename="t/t_xml_flat_pub_mod.v" language="1800-2017"/> <file id="d" filename="t/t_xml_flat_pub_mod.v" language="1800-2023"/>
</module_files> </module_files>
<cells> <cells>
<cell loc="d,11,8,11,11" name="$root" submodname="$root" hier="$root"/> <cell loc="d,11,8,11,11" name="$root" submodname="$root" hier="$root"/>

10
test_regress/t/t_xml_flat_vlvbound.out
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@ -2,13 +2,13 @@
<!-- DESCRIPTION: Verilator output: XML representation of netlist --> <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml> <verilator_xml>
<files> <files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/> <file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/> <file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2017"/> <file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_flat_vlvbound.v" language="1800-2017"/> <file id="d" filename="t/t_xml_flat_vlvbound.v" language="1800-2023"/>
</files> </files>
<module_files> <module_files>
<file id="d" filename="t/t_xml_flat_vlvbound.v" language="1800-2017"/> <file id="d" filename="t/t_xml_flat_vlvbound.v" language="1800-2023"/>
</module_files> </module_files>
<cells> <cells>
<cell loc="d,7,8,7,21" name="$root" submodname="$root" hier="$root"/> <cell loc="d,7,8,7,21" name="$root" submodname="$root" hier="$root"/>

10
test_regress/t/t_xml_output.out
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@ -2,13 +2,13 @@
<!-- DESCRIPTION: Verilator output: XML representation of netlist --> <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml> <verilator_xml>
<files> <files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/> <file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/> <file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2017"/> <file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_output.v" language="1800-2017"/> <file id="d" filename="t/t_xml_output.v" language="1800-2023"/>
</files> </files>
<module_files> <module_files>
<file id="d" filename="t/t_xml_output.v" language="1800-2017"/> <file id="d" filename="t/t_xml_output.v" language="1800-2023"/>
</module_files> </module_files>
<cells> <cells>
<cell loc="d,7,8,7,9" name="m" submodname="m" hier="m"/> <cell loc="d,7,8,7,9" name="m" submodname="m" hier="m"/>

10
test_regress/t/t_xml_tag.out
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@ -2,13 +2,13 @@
<!-- DESCRIPTION: Verilator output: XML representation of netlist --> <!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml> <verilator_xml>
<files> <files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/> <file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/> <file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2017"/> <file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_tag.v" language="1800-2017"/> <file id="d" filename="t/t_xml_tag.v" language="1800-2023"/>
</files> </files>
<module_files> <module_files>
<file id="d" filename="t/t_xml_tag.v" language="1800-2017"/> <file id="d" filename="t/t_xml_tag.v" language="1800-2023"/>
</module_files> </module_files>
<cells> <cells>
<cell loc="d,12,8,12,9" name="m" submodname="m" hier="m"> <cell loc="d,12,8,12,9" name="m" submodname="m" hier="m">