Fix --main --trace missing initial timestep (#3678).

src/V3EmitCMain.cpp

@@ -74,10 +74,6 @@ private:
              + "{contextp.get()}};\n");
         puts("\n");
 
-        puts("// Evaluate initials\n");
-        puts("topp->eval();  // Evaluate\n");
-        puts("\n");
-
         puts("// Simulate until $finish\n");
         puts("while (!contextp->gotFinish()) {\n");
         puts(/**/ "// Evaluate model\n");

test_regress/t/t_timing_debug1.out

@@ -67,14 +67,6 @@
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
--V{t#,#}         No triggers active
--V{t#,#}+    Vt_timing_debug1___024root___timing_commit
--V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
--V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
--V{t#,#}+ Eval
--V{t#,#}+    Vt_timing_debug1___024root___eval
--V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
--V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         'act' region trigger index 4 is active: @([true] __VdlySched.awaitingCurrentTime())
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
 -V{t#,#}+    Vt_timing_debug1___024root___timing_resume

test_regress/t/t_timing_debug2.out

@@ -30,14 +30,6 @@
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
 -V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
--V{t#,#}         No triggers active
--V{t#,#}+    Vt_timing_debug2___024root___timing_commit
--V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
--V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
--V{t#,#}+ Eval
--V{t#,#}+    Vt_timing_debug2___024root___eval
--V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
--V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
 -V{t#,#}         'act' region trigger index 0 is active: @([true] __VdlySched.awaitingCurrentTime())
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
 -V{t#,#}+    Vt_timing_debug2___024root___timing_resume

test_regress/t/t_trace_timing1.out

@@ -0,0 +1,27 @@
+$version Generated by VerilatedVcd $end
+$date Sat Oct 15 13:17:45 2022 $end
+$timescale 1ps $end
+
+ $scope module TOP $end
+  $scope module t $end
+   $var wire 32 % CLOCK_CYCLE [31:0] $end
+   $var wire  1 $ clk $end
+   $var wire  1 # rst $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+1#
+0$
+b00000000000000000000000000001010 %
+#5
+1$
+#10
+0#
+0$
+#15
+1$
+#20
+1#

test_regress/t/t_trace_timing1.pl

@@ -0,0 +1,35 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    compile(
+        verilator_flags => [# Custom as don't want -cc
+                            "-Mdir $Self->{obj_dir}",
+                            "--debug-check", ],
+        verilator_flags2 => ['--binary --trace'],
+        verilator_make_cmake => 0,
+        verilator_make_gmake => 0,
+        make_main => 0,
+        );
+
+    execute(
+        check_finished => 1,
+        );
+}
+
+vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
+
+ok(1);
+1;

test_regress/t/t_trace_timing1.v

@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define STRINGIFY(x) `"x`"
+
+module t(/*AUTOARG*/);
+
+   localparam CLOCK_CYCLE = 10;
+
+   logic rst;
+   logic clk;
+
+   initial begin
+      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+      $dumpvars;
+   end
+
+   always #(CLOCK_CYCLE/2) clk = ~clk;
+
+   always begin
+      rst = 1;
+      clk = 0;
+      $display("[%0t] rst: %d, rst: %d", $time, rst, rst);
+
+      #CLOCK_CYCLE;
+      rst = 0;
+      $display("[%0t] rst: %d, rst: %d", $time, rst, rst);
+
+      #CLOCK_CYCLE;
+      $display("[%0t] rst: %d, rst: %d", $time, rst, rst);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule