Fix name collision on unnamed blocks, bug567.

Changes

@@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.84** devel
 
+****  Add -x-initial-edge, bug570.  [Jeremy Bennett]
+
 ****  Fix parameter pins interspersed with cells broke in 3.840.  [Bernard Deadman]
 
 ****  Fix large shift error on large shift constants.  [David Welch]
@@ -13,7 +15,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix missing var access functions when no DPI, bug572. [Amir Gonnen]
 
-****  Add -x-initial-edge, bug570.  [Jeremy Bennett]
+****  Fix name collision on unnamed blocks, bug567.  [Chandan Egbert]
 
 
 * Verilator 3.841 2012/09/03

src/V3LinkDot.cpp

@@ -451,6 +451,9 @@ private:
 	string oldscope = m_scope;
 	VSymEnt* oldModSymp = m_modSymp;
 	VSymEnt* oldCurSymp = m_curSymp;
+        int      oldParamNum    = m_paramNum;
+        int      oldBeginNum    = m_beginNum;
+        int      oldModBeginNum = m_modBeginNum;
 	if (doit) {
 	    UINFO(2,"     Link Module: "<<nodep<<endl);
 	    if (nodep->dead()) nodep->v3fatalSrc("Module in cell tree mislabeled as dead?");
@@ -482,6 +485,9 @@ private:
 	m_scope = oldscope;
 	m_modSymp = oldModSymp;
 	m_curSymp = oldCurSymp;
+        m_paramNum    = oldParamNum;
+        m_beginNum    = oldBeginNum;
+        m_modBeginNum = oldModBeginNum;
 	// Prep for next
 	m_packagep = NULL;
     }

test_regress/t/t_hierarchy_unnamed.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    v_flags2 => ["--lint-only"],
+    make_top_shell => 0,
+    make_main => 0,
+    verilator_make_gcc => 0,
+    );
+
+ok(1);
+1;

test_regress/t/t_hierarchy_unnamed.v

@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Chandan Egbert.
+
+module sub();
+endmodule
+
+module t(input logic a, input logic b,
+	 output logic x, output logic y);
+
+   always_comb begin
+      integer i;
+      x = a;
+   end
+
+   sub u0();
+
+   always_comb begin
+      integer j;
+      y = b;
+   end
+
+endmodule