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Commentary: Fix sphinx doc warnings

This commit is contained in:
Wilson Snyder 2022-10-02 16:47:32 -04:00
parent 4367e03e46
commit 90009b9ec7
4 changed files with 8 additions and 7 deletions
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1
docs/guide/connecting.rst
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@ -451,6 +451,7 @@ the user should call:
* :code:`designp->nextTimeSlot()`, which returns the simulation time of the * :code:`designp->nextTimeSlot()`, which returns the simulation time of the
next delayed event. This method can only be called if next delayed event. This method can only be called if
:code:`designp->nextTimeSlot()` returned :code:`true`. :code:`designp->nextTimeSlot()` returned :code:`true`.
Call :code:`eventsPending()` to check if you should continue with the Call :code:`eventsPending()` to check if you should continue with the
simulation, and then :code:`nextTimeSlot()` to move simulation time forward. simulation, and then :code:`nextTimeSlot()` to move simulation time forward.
:vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic example :vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic example

8
docs/guide/example_binary.rst
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@ -1,10 +1,10 @@
.. Copyright 2003-2022 by Wilson Snyder. .. Copyright 2003-2022 by Wilson Snyder.
.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
.. _Example C++ Execution: .. _Example Create-Binary Execution:
Example C++ Execution Example Create-Binary Execution
===================== ===============================
We'll compile this SystemC example into a Verilated simulation binary. For We'll compile this SystemC example into a Verilated simulation binary. For
an example that discusses the next level of detail see :ref:`Example C++ an example that discusses the next level of detail see :ref:`Example C++
@ -36,7 +36,7 @@ Breaking this command down:
#. :vlopt:`--binary` telling Verilator to do everything needed to create a #. :vlopt:`--binary` telling Verilator to do everything needed to create a
simulation executable. simulation executable.
#. :vlopt:`-j` `0' to Verilate using use as many CPU threads as the machine #. :vlopt:`-j` `0` to Verilate using use as many CPU threads as the machine
has. has.
#. :vlopt:`-Wall` so Verilator has stronger lint warnings #. :vlopt:`-Wall` so Verilator has stronger lint warnings

2
docs/guide/exe_sim.rst
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@ -72,7 +72,7 @@ Summary:
.. option:: +verilator+prof+threads+window+<value> .. option:: +verilator+prof+threads+window+<value>
Deprecated. Alias for :vlopt:`+verilator+prof+exec+window+\<filename\>` Deprecated. Alias for :vlopt:`+verilator+prof+exec+window+\<value\>`
.. option:: +verilator+prof+vlt+file+<filename> .. option:: +verilator+prof+vlt+file+<filename>

4
docs/guide/exe_verilator.rst
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@ -421,8 +421,8 @@ Summary:
Rarely needed - for developer use. Set the dumping level in the Rarely needed - for developer use. Set the dumping level in the
specified Verilator source file to the specified value (e.g. specified Verilator source file to the specified value (e.g.
:vlopt:`--dumpi-V3Order 9`). Level 0 disables dumps and is equivalent `--dumpi-V3Order 9`). Level 0 disables dumps and is equivalent to
to :vlopt:`--no-dump-<srcfile>`. Level 9 enables dumping of everything. `--no-dump-<srcfile>`. Level 9 enables dumping of everything.
.. option:: -E .. option:: -E