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Tests: Add t_sv_cpu, bug473. By Jeremy Bennett.

This commit is contained in:
Wilson Snyder 2012-05-16 18:38:01 -04:00
parent 3e623b8959
commit 8d960a2eb9
21 changed files with 1734 additions and 0 deletions
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45
test_regress/t/t_sv_cpu.pl Executable file
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#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett,
# Embecosm.
$Self->{vlt} and $Self->unsupported("Verilator unsupported");
compile (
# Taken from the original VCS command line.
v_flags2 => ["t/t_sv_cpu_code/timescale.sv",
"t/t_sv_cpu_code/program_h.sv",
"t/t_sv_cpu_code/pads_h.sv",
"t/t_sv_cpu_code/ports_h.sv",
"t/t_sv_cpu_code/pinout_h.sv",
"t/t_sv_cpu_code/genbus_if.sv",
"t/t_sv_cpu_code/pads_if.sv",
"t/t_sv_cpu_code/adrdec.sv",
"t/t_sv_cpu_code/pad_gpio.sv",
"t/t_sv_cpu_code/pad_vdd.sv",
"t/t_sv_cpu_code/pad_gnd.sv",
"t/t_sv_cpu_code/pads.sv",
"t/t_sv_cpu_code/ports.sv",
"t/t_sv_cpu_code/ac_dig.sv",
"t/t_sv_cpu_code/ac_ana.sv",
"t/t_sv_cpu_code/ac.sv",
"t/t_sv_cpu_code/cpu.sv",
"t/t_sv_cpu_code/chip.sv"],
vcs_flags2 => ["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"],
verilator_flags2 => ["-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"],
iv_flags2 => ["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"],
);
execute (
check_finished=>1,
);
ok(1);
1;

142
test_regress/t/t_sv_cpu.v Normal file
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// DESCRIPTION: Verilator: System Verilog test of a complete CPU
//
// This code instantiates and runs a simple CPU written in System Verilog.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// **************************************************************************
// Regs and Wires
// **************************************************************************
reg rst;
integer rst_count;
integer clk_count;
testbench testbench_i (/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// **************************************************************************
// Reset Generation
// **************************************************************************
initial begin
rst = 1'b1;
rst_count = 0;
end
always @( posedge clk ) begin
if (rst_count < 2) begin
rst_count++;
end
else begin
rst = 1'b0;
end
end
// **************************************************************************
// Drive simulation for 500 clock cycles
// **************************************************************************
initial begin
`ifdef TEST_VERBOSE
$display( "[testbench] - Start of simulation ----------------------- " );
`endif
clk_count = 0;
end
always @( posedge clk ) begin
if (500 == clk_count) begin
$finish ();
end
else begin
clk_count++;
end
end
final begin
`ifdef TEST_VERBOSE
$display( "[testbench] - End of simulation ------------------------- " );
`endif
$write("*-* All Finished *-*\n");
end
endmodule
module testbench (/*AUTOARG*/
// Inputs
clk, rst
);
input clk;
input rst;
// **************************************************************************
// Local parameters
// **************************************************************************
localparam
NUMPADS = $size( pinout );
// **************************************************************************
// Regs and Wires
// **************************************************************************
// **** Pinout ****
wire pad [1:NUMPADS]; // GPIO Pads (PORT{A,...,R}).
// **************************************************************************
// Regs and Wires, Automatics
// **************************************************************************
/*AUTOWIRE*/
// **************************************************************************
// Includes (Testbench extensions)
// **************************************************************************
// N/A
// **************************************************************************
// Chip Instance
// **************************************************************************
chip
i_chip
(
/*AUTOINST*/
// Inouts
.pad (pad),
// Inputs
.clk (clk),
.rst (rst));
endmodule // test
// Local Variables:
// verilog-library-directories:("." "t_sv_cpu_code")
// End:

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test_regress/t/t_sv_cpu_code/ac.sv Normal file
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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
module ac
#( parameter
ID = 1 )
(
// ***************************************************************************
// Module Interface (interfaces, outputs, and inputs)
// ***************************************************************************
// **** Interfaces ****
genbus_if.slave dbus,
pads_if.mp_ana padsif,
// - System -
input logic clk,
input logic rst
);
// ***************************************************************************
// Regs and Wires, Automatics
// ***************************************************************************
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic acenable; // From i_ac_dig of ac_dig.v
logic acout; // From i_ac_ana of ac_ana.v
// End of automatics
// ***************************************************************************
// Digital Control
// ***************************************************************************
ac_dig
#( .ID(ID) )
i_ac_dig
(
.dbus (dbus),
/*AUTOINST*/
// Outputs
.acenable (acenable),
// Inputs
.acout (acout),
.clk (clk),
.rst (rst));
// ***************************************************************************
// Analog Model
// ***************************************************************************
ac_ana
i_ac_ana
(
.padsif (padsif),
/*AUTOINST*/
// Outputs
.acout (acout),
// Inputs
.acenable (acenable),
.clk (clk),
.rst (rst));
endmodule // ac

43
test_regress/t/t_sv_cpu_code/ac_ana.sv Normal file
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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
module ac_ana
// #( parameter
// ID = 1 )
(
// ***************************************************************************
// Module Interface (interfaces, outputs, and inputs)
// ***************************************************************************
// **** Interfaces ****
pads_if.mp_ana padsif,
// **** Outputs ****
output logic acout,
// **** Inputs ****
input logic acenable,
// - System -
input logic clk,
input logic rst
);
// ***************************************************************************
// Analog Model
// ***************************************************************************
assign acout = (padsif.ana[1] - padsif.ana[2]) & acenable;
assign padsif.ana_override[1] = 1'b0;
assign padsif.ana_override[2] = 1'b0;
endmodule // ac_ana

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test_regress/t/t_sv_cpu_code/ac_dig.sv Normal file
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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
module ac_dig
#( parameter
ID = 1 )
(
// ***************************************************************************
// Module Interface (interfaces, outputs, and inputs)
// ***************************************************************************
// **** Interfaces ****
genbus_if.slave dbus,
// **** Outputs ****
output logic acenable,
// **** Inputs ****
input logic acout,
// - System -
input logic clk,
input logic rst
);
// ***************************************************************************
// Regs and Wires
// ***************************************************************************
// **** Internal Data Bus ****
logic [15:0] sdata;
logic ws;
logic [15:0] mdata;
logic [15:0] adr;
logic [1:0] we;
logic [1:0] re;
// **** User Registers ****
struct packed
{
logic [7:1] reserved;
logic enable;
} control;
struct packed
{
logic [7:1] reserved;
logic acout;
} status;
// **** Internals ****
logic [1:0] sync;
// ***************************************************************************
// Assignments
// ***************************************************************************
assign acenable = control.enable;
// ***************************************************************************
// "dbus" Connection
// ***************************************************************************
always_comb
begin
dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr[1:0]), .we(we), .re(re) );
// dbus.sConnect( ID, rst, sdata, ws, mdata, adr, we, re );
end
// ***************************************************************************
// Register Access
// ***************************************************************************
// **** Register Write ****
always_ff @( posedge clk )
begin
if ( rst )
control <= 8'h00;
else if ( (adr[1:0] == 2'b00) & we[0] )
control <= mdata[7:0];
end
// **** Regiser Read ****
always_comb
begin: RegisterRead
// - Local Variables -
logic [7:0] data[0:3]; // Read access concatination.
// - Setup read multiplexer -
data = '{ control,
status,
8'h00,
8'h00 };
// - Connect "genbusif" -
sdata = { 8'h00, data[ adr[1:0] ] };
ws = 1'b0;
end
// ***************************************************************************
// Status
// ***************************************************************************
// **** Synchronization ****
always_ff @( posedge clk )
begin
if ( rst )
sync <= 2'b00;
else if ( control.enable )
sync <= {sync[0], acout};
end
always_comb
begin
// - Defaults -
status = {$size(status){1'b0}};
// - Set register values -
status.acout = sync[1];
end
endmodule // ac_dig

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test_regress/t/t_sv_cpu_code/adrdec.sv Normal file
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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
module adrdec
#( parameter
NSLAVES = 2 )
(
// ***************************************************************************
// Module Interface (interfaces, outputs, and inputs)
// ***************************************************************************
// **** Interfaces ****
genbus_if.adrdec dbus
);
// ***************************************************************************
// Address Decode
// ***************************************************************************
// const logic [15:0] adrmap[1:2] = '{}
always_comb
begin
logic sel [1:NSLAVES];
sel[1] = (dbus.s_adr[1][7:4] == 4'h0);
sel[2] = (dbus.s_adr[2][7:4] == 4'h1);
// sel[3] = (dbus.s_adr[3][7:4] == 4'h2);
dbus.s_sel = sel;
// for ( i = 1; i <= dbus.aNumSlaves; i++ )
// begin
// dbus.s_sel[i] = (dbus.s_adr[i] == adrmap[i]);
// end
end
endmodule // adrdec

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test_regress/t/t_sv_cpu_code/chip.sv Normal file
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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
// *****************************************************************************
// Top level of System Verilog evalution (Full chip level)
// *****************************************************************************
module chip
#( parameter
NUMPADS = $size( pinout )
)
(
// **** Pinout ****
inout wire pad [1:NUMPADS],
// **** Inputs !!!! ****
input logic clk,
input logic rst
);
// ***************************************************************************
// Local Parameters
// ***************************************************************************
localparam
NSLAVES = 2;
// ***************************************************************************
// PADS
// ***************************************************************************
// **** Interface ****
pads_if
padsif();
// **** Pad Instansiations ****
pads
// #( )
i_pads
(
/*AUTOINST*/
// Interfaces
.padsif (padsif.mp_pads),
// Inouts
.pad (pad),
// Inputs
.clk (clk),
.rst (rst));
// ***************************************************************************
// "dbus" Interface
// ***************************************************************************
genbus_if
#( .NSLAVES(NSLAVES) )
dbus( .clk(clk), .rst(rst), .test_mode(1'b0) );
adrdec
// #( )
i_adrdec
(
/*AUTOINST*/
// Interfaces
.dbus (dbus.adrdec));
// ***************************************************************************
// CPU ("dbus" Master)
// ***************************************************************************
cpu
#( .ID(1) )
i_cpu
(
/*AUTOINST*/
// Interfaces
.dbus (dbus.master),
// Inputs
.clk (clk),
.rst (rst));
// ***************************************************************************
// PORTS ("dbus" Slave #1)
// ***************************************************************************
ports
#( .ID(1) )
i_ports
(
/*AUTOINST*/
// Interfaces
.dbus (dbus.slave),
.padsif (padsif.mp_dig),
// Inputs
.clk (clk),
.rst (rst));
// ***************************************************************************
// Analog Comparator ("dbus" Slave #2)
// ***************************************************************************
ac
#( .ID(2) )
i_ac
(
/*AUTOINST*/
// Interfaces
.dbus (dbus.slave),
.padsif (padsif.mp_ana),
// Inputs
.clk (clk),
.rst (rst));
endmodule // chip

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test_regress/t/t_sv_cpu_code/cpu.sv Normal file
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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
module cpu
#( parameter
// ...
ID = 1 ) // Not used!
(
// ***************************************************************************
// Module Interface (interfaces, outputs, and inputs)
// ***************************************************************************
// **** Interfaces ****
genbus_if.master dbus,
// **** Outputs ****
// N/A
// **** Inputs ****
input logic clk,
input logic rst
);
// ***************************************************************************
// Regs and Wires
// ***************************************************************************
// **** Program Memory ****
logic [15:0] rom_out;
// **** Register File (RF) ****
logic [7:0] rf[0:15];
// **** Fetch Stage ****
logic [7:0] pc; // PC -> Program counter.
logic [15:0] ir; // IR -> Instruction Register.
// **** Decode ****
logic [3:0] idec_rd;
logic idec_rd_we;
logic [7:0] idec_rd_data;
logic [3:0] idec_rs;
logic [7:0] idec_nextpc; // New PC if change of program flow.
logic idec_coff; // Indicates a change of program flow.
logic [7:0] idec_mem_adr;
logic idec_mem_re;
logic idec_mem_we;
// **** Memory ****
logic [7:0] mem_data; // Data from peripheral.
logic mem_ws; // Waitstate.
// ***************************************************************************
// Program Memory (ROM) Interface
// ***************************************************************************
always_comb
begin: ROM
// - Local Variables -
integer i;
reg [15:0] irom [0:255];
// - Set default -
for ( i = 0; i < 256; i++ )
begin
if ( i < $size(rom) )
irom[i] = rom[i];
else
irom[i] = 16'h0000;
end
rom_out = irom[pc[7:0]];
end
// ***************************************************************************
// Register File (RF)
// ***************************************************************************
always_ff @( posedge clk )
begin: RegFile
// - Local Variables -
integer i;
// - Register File -
for ( i = 0; i < 16; i++ )
begin
if ( rst )
rf[i][7:0] <= 8'h00;
else if ( idec_rd_we & (idec_rd == i[3:0]) )
rf[i] <= idec_rd_data;
end
end
// ***************************************************************************
// Fetch Stage
// ***************************************************************************
// **** Program Counter (PC) / Instruction Register (IR) ****
always_ff @( posedge clk )
begin
if ( rst )
begin
pc <= 8'h00;
ir <= 16'h0000;
end
else //if ( ~mem_ws )
begin
if ( ~idec_coff )
begin
pc <= pc + 1;
ir <= rom_out; // Fetch Instruction.
end
else
begin
pc <= idec_nextpc;
ir <= 16'h0000; // Insert no operation (NOP).
end
end
end
// ***************************************************************************
// Decode/Execute Stage
// ***************************************************************************
always_comb
begin
// - Defaults -
idec_rd = 4'h0;
idec_rd_we = 1'b0;
idec_rd_data = 8'h00;
idec_rs = 4'h0;
idec_nextpc = 8'h00;
idec_coff = 1'b0;
idec_mem_adr = 8'h00;
idec_mem_re = 1'b0;
idec_mem_we = 1'b0;
casez ( ir )
16'h0000:; // NOP (<=> Default)
16'h1???: // JMP imm
begin
idec_nextpc = ir[7:0];
idec_coff = 1'b1;
end
16'h4???: // LDI rd, imm
begin
idec_rd = ir[8+:4];
idec_rd_we = 1'b1;
idec_rd_data = ir[0+:8];
end
16'h8???:
begin // STS imm, rs
idec_mem_adr = ir[0+:8];
idec_mem_we = 1'b1;
idec_rs = ir[8+:4];
end
16'h9???:
begin // LDS rd, imm
idec_mem_adr = ir[0+:8];
idec_mem_we = 1'b1;
idec_rd = ir[8+:4];
idec_rd_we = 1'b1;
idec_rd_data = mem_data[0+:8];
end
endcase
end
// ***************************************************************************
// Memory Access ("Stage")
// ***************************************************************************
// **** Connect to "dbus" ****
always_comb
begin: Conntect
reg [15:0] sdata16;
dbus.mConnect
( ID, // ID
sdata16, // sdata
mem_ws, // ws
{2{rf[idec_rs]}}, // mdata
// adr
{8'h00, idec_mem_adr[7:1], 1'b0},
// we
{idec_mem_adr[0],~idec_mem_adr[0]} & {2{idec_mem_we}},
// re
{idec_mem_adr[0],~idec_mem_adr[0]} & {2{idec_mem_re}}
);
// - Connect 16-bit databus to 8-bit CPU -
mem_data = ( idec_mem_adr[0] ) ? sdata16[15:8] : sdata16[7:0];
end
mPreAdrDecode_resp busproperty;
always_comb
begin: PreAdrDecode
busproperty = dbus.mPreAdrDecode( 0, idec_mem_adr );
end
endmodule // cpu

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test_regress/t/t_sv_cpu_code/genbus_if.sv Normal file
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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
typedef struct packed
{
bit [1:0] size;
} mPreAdrDecode_resp;
interface genbus_if
#( parameter
DSIZE = 2,
SSIZE = DSIZE,
ASIZE = 16,
NMASTERS = 1,
NSLAVES = 1,
DMSB = (DSIZE<<3) - 1,
SMSB = SSIZE - 1,
AMSB = ASIZE - 1
)
(
// **** Inputs ****
// - System -
input logic clk, // Device Clock.
input logic rst, // Device Reset.
input logic test_mode // Test mode.
);
// ***************************************************************************
// Interface Variables
// ***************************************************************************
// **** Master ****
logic [DMSB:0] m_sdata[1:NMASTERS]; // Slave data.
logic m_ws [1:NMASTERS]; // Slave wait state.
logic [DMSB:0] m_mdata[1:NMASTERS]; // Master data.
logic [AMSB:0] m_adr [1:NMASTERS]; // Address.
logic [SMSB:0] m_we [1:NMASTERS]; // Write enable.
logic [SMSB:0] m_re [1:NMASTERS]; // Read enable.
// **** Slave ****
logic [DMSB:0] s_sdata[1:NSLAVES]; // Slave data (from slave).
logic s_ws [1:NSLAVES]; // Slave wait state (from slave).
logic [DMSB:0] s_mdata[1:NSLAVES]; // Master data (to slave).
logic [AMSB:0] s_adr [1:NSLAVES]; // Address (to slave).
logic [SMSB:0] s_we [1:NSLAVES]; // Write enable (to slave).
logic [SMSB:0] s_re [1:NSLAVES]; // Read enable (to slave).
// **** Address Decoder ****
logic s_sel [1:NSLAVES]; // Slave select (to slave).
// ***************************************************************************
// Modports
// ***************************************************************************
modport master(
import mConnect,
import mPreAdrDecode,
input m_sdata,
input m_ws,
output m_mdata,
output m_adr,
output m_we,
output m_re
);
// - Slaves -
modport slave(
import sConnect,
output s_sdata,
output s_ws,
input s_mdata,
input s_adr,
input s_we,
input s_re,
input s_sel
);
// UNSUPPORTED
// for (genvar i = 1; i <= NSLAVES; i++ )
// begin: mps
// modport slave(
// import sConnect,
// output .s_sdata( s_sdata[i] ),
// output .s_ws ( s_ws [i] ),
// input .s_mdata( s_mdata[i] ),
// input .s_adr ( s_adr [i] ),
// input .s_we ( s_we [i] ),
// input .s_re ( s_re [i] ),
// input .s_sel ( s_sel [i] )
// );
// end
// blocks
modport adrdec(
import aNumSlaves,
input s_adr,
output s_sel
);
// ***************************************************************************
// Bus Multiplexers
// ***************************************************************************
always_comb
begin: busmux
// - Local Variables -
integer i;
// - Defautls -
m_sdata[1] = {(DSIZE<<3){1'b0}};
m_ws [1] = 1'b0;
for ( i = 1; i <= NSLAVES; i++ )
begin
m_sdata[1] |= s_sdata[i];
m_ws [1] |= s_ws [i];
s_mdata[i] = m_mdata[1];
s_adr [i] = m_adr [1];
s_we [i] = m_we [1];
s_re [i] = m_re [1];
end
end
// ***************************************************************************
// Master Functions and Tasks
// ***************************************************************************
function automatic void mConnect( input integer id,
output logic [DMSB:0] sdata,
output logic ws,
input logic [DMSB:0] mdata,
input logic [AMSB:0] adr,
input logic [SMSB:0] we,
input logic [SMSB:0] re );
begin
m_mdata[id] = mdata;
m_adr [id] = adr;
m_we [id] = we;
m_re [id] = re;
sdata = m_sdata[id];
ws = m_ws [id];
end
endfunction
function automatic mPreAdrDecode_resp mPreAdrDecode( input integer id,
input logic [AMSB:0] adr );
begin
// ToDo: Add parameterized address decoding!!!!
// Example code:
if ( adr[0] )
mPreAdrDecode.size = 2'b01; // Word (16-bit) memory.
else
mPreAdrDecode.size = 2'b10; // Double Word (32-bit) memory.
end
endfunction
// ***************************************************************************
// Slave Functions and Tasks
// ***************************************************************************
function automatic void sConnect( input integer id,
input logic rst,
input logic [DMSB:0] sdata,
input logic ws,
output logic [DMSB:0] mdata,
output logic [AMSB:0] adr,
output logic [SMSB:0] we,
output logic [SMSB:0] re );
begin
s_sdata[id] = sdata & {(DSIZE<<3){s_sel[id]}};
s_ws [id] = ws & {SSIZE{s_sel[id]}};
mdata = s_mdata[id] & {16{~rst}};
adr = s_adr [id];
we = (s_we [id] & {SSIZE{s_sel[id]}}) | {SSIZE{rst}};
re = s_re [id] & {SSIZE{s_sel[id]}};
end
endfunction
// ***************************************************************************
// Address Decoder Functions and Tasks
// ***************************************************************************
function automatic integer aNumSlaves;
aNumSlaves = NSLAVES;
endfunction
endinterface // genbus_if

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test_regress/t/t_sv_cpu_code/pad_gnd.sv Normal file
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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
//*****************************************************************************
// PAD_GND - Ground Supply Pad (Dummy!!!!)
//*****************************************************************************
module pad_gnd
#( parameter ID = 0 )
(
inout wire pad
);
assign pad = 1'b0;
endmodule // pad_gnd

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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
//*****************************************************************************
// PAD_GPIO - General Purpose I/O Pad (Dummy!!!!)
//*****************************************************************************
module pad_gpio
#( parameter ID = 0 )
(
input logic pullup_en,
input logic pulldown_en,
input logic output_en,
input logic output_val,
input logic slew_limit_en,
input logic input_en,
output logic input_val,
inout wire ana,
inout wire pad
);
// **** Analog <-> pad connection ****
alias ana = pad;
// **** Digital driver <-> pad connection ****
assign pad = (output_en) ? output_val : 1'bz;
// **** Digital pull-up/pull-down <-> pad connection ****
// TO BE ADDED!!!!
// **** Digital input <-> pad connection ****
assign input_val = (input_en) ? pad : 1'b0;
endmodule // pad_gpio

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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
//*****************************************************************************
// PAD_VDD - VDD Supply Pad (Dummy!!!!)
//*****************************************************************************
module pad_vdd
#( parameter ID = 0 )
(
inout wire pad
);
assign pad = 1'b1;
endmodule // pad_vdd

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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
module pads
#( parameter
NUMPADS = $size( pinout )
)
(
// ***************************************************************************
// Module Interface
// ***************************************************************************
// **** Interfaces ****
pads_if.mp_pads padsif,
// **** Pinout ****
inout wire pad [1:NUMPADS],
// **** Inputs ****
input logic clk,
input logic rst
);
// ***************************************************************************
// Code Section
// ***************************************************************************
genvar i;
for ( i = 1; i <= NUMPADS; i++ )
begin
`ifdef VCS
localparam t_padtype p_type = t_padtype'(pinout_wa[i][pinout_wa_padtype]);
localparam t_pinid p_id = t_pinid'(pinout_wa[i][pinout_wa_id]);
`else
localparam t_padtype p_type = pinout[i].padtype;
localparam t_pinid p_id = pinout[i].id;
`endif
case ( p_type )
PADTYPE_GPIO:
pad_gpio #( .ID( i ) )
i_pad_gpio(.pad (pad [i]),
// Outputs
.input_val (padsif.input_val [i]),
// Inouts
.ana (padsif.ana [i]),
// Inputs
.pullup_en (padsif.pullup_en [i]),
.pulldown_en (padsif.pulldown_en [i]),
.output_en (padsif.output_en [i]),
.output_val (padsif.output_val [i]),
.slew_limit_en (padsif.slew_limit_en[i]),
.input_en (padsif.input_en [i])
/*AUTOINST*/);
PADTYPE_VDD:
begin
pad_vdd #( .ID( i ) )
i_pad_vdd(.pad (pad[i])
/*AUTOINST*/);
// Not SV standard, yet... assign padsif.input_val[i] = ();
end
PADTYPE_GND:
begin
pad_gnd #( .ID( i ) )
i_pad_gnd(.pad (pad[i])
/*AUTOINST*/);
end
endcase
end
endmodule // pads

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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
`ifndef _PADS_H_SV_
`define _PADS_H_SV_
// *****************************************************************************
//
// *****************************************************************************
// **** Pin Identifiers ****
typedef enum int
{
PINID_A0 = 32'd0, // MUST BE ZERO!
// - Standard Ports -
PINID_A1, PINID_A2, PINID_A3, PINID_A4, PINID_A5, PINID_A6, PINID_A7,
PINID_B0, PINID_B1, PINID_B2, PINID_B3, PINID_B4, PINID_B5, PINID_B6, PINID_B7,
PINID_C0, PINID_C1, PINID_C2, PINID_C3, PINID_C4, PINID_C5, PINID_C6, PINID_C7,
PINID_D0, PINID_D1, PINID_D2, PINID_D3, PINID_D4, PINID_D5, PINID_D6, PINID_D7,
PINID_E0, PINID_E1, PINID_E2, PINID_E3, PINID_E4, PINID_E5, PINID_E6, PINID_E7,
PINID_F0, PINID_F1, PINID_F2, PINID_F3, PINID_F4, PINID_F5, PINID_F6, PINID_F7,
PINID_G0, PINID_G1, PINID_G2, PINID_G3, PINID_G4, PINID_G5, PINID_G6, PINID_G7,
PINID_H0, PINID_H1, PINID_H2, PINID_H3, PINID_H4, PINID_H5, PINID_H6, PINID_H7,
// PINID_I0, PINID_I1, PINID_I2, PINID_I3, PINID_I4, PINID_I5, PINID_I6, PINID_I7,-> DO NOT USE!!!! I == 1
PINID_J0, PINID_J1, PINID_J2, PINID_J3, PINID_J4, PINID_J5, PINID_J6, PINID_J7,
PINID_K0, PINID_K1, PINID_K2, PINID_K3, PINID_K4, PINID_K5, PINID_K6, PINID_K7,
PINID_L0, PINID_L1, PINID_L2, PINID_L3, PINID_L4, PINID_L5, PINID_L6, PINID_L7,
PINID_M0, PINID_M1, PINID_M2, PINID_M3, PINID_M4, PINID_M5, PINID_M6, PINID_M7,
PINID_N0, PINID_N1, PINID_N2, PINID_N3, PINID_N4, PINID_N5, PINID_N6, PINID_N7,
// PINID_O0, PINID_O1, PINID_O2, PINID_O3, PINID_O4, PINID_O5, PINID_O6, PINID_O7,-> DO NOT USE!!!! O == 0
PINID_P0, PINID_P1, PINID_P2, PINID_P3, PINID_P4, PINID_P5, PINID_P6, PINID_P7,
PINID_Q0, PINID_Q1, PINID_Q2, PINID_Q3, PINID_Q4, PINID_Q5, PINID_Q6, PINID_Q7,
PINID_R0, PINID_R1, PINID_R2, PINID_R3, PINID_R4, PINID_R5, PINID_R6, PINID_R7,
// - AUX Port (Custom) -
PINID_X0, PINID_X1, PINID_X2, PINID_X3, PINID_X4, PINID_X5, PINID_X6, PINID_X7,
// - PDI Port -
PINID_D2W_DAT, PINID_D2W_CLK,
// - Power Pins -
PINID_VDD0, PINID_VDD1, PINID_VDD2, PINID_VDD3,
PINID_GND0, PINID_GND1, PINID_GND2, PINID_GND3,
// - Maximum number of pins -
PINID_MAX
} t_pinid;
// **** Pad types ****
typedef enum int
{
PADTYPE_DEFAULT = 32'd0,
PADTYPE_GPIO, // General Purpose I/O Pad (GPIO).
PADTYPE_GPIO_ANA, // GPIO with Analog connection. Low noise GPIO.
PADTYPE_GPIO_HDS, // GPIO with High Drive Strength.
PADTYPE_VDD, // VDD Supply Pad
PADTYPE_GND // Ground Pad
} t_padtype;
`endif // !`ifdef _PADS_H_SV_

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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
interface pads_if();
// ***************************************************************************
// Local Parameters
// ***************************************************************************
localparam
NUMPADS = $size( pinout );
// ***************************************************************************
// Interface Variables
// ***************************************************************************
// - PADS Digital Interface -
logic pullup_en [1:NUMPADS];// Pull-up/down/bus-keeper enable.
logic pulldown_en [1:NUMPADS];// Pull direction (0:Pull-up; 1:Pull-down).
logic output_en [1:NUMPADS];// Digital output buffer enable.
logic output_val [1:NUMPADS];// Digital output value.
logic input_en [1:NUMPADS];// Digital input buffer enable.
logic slew_limit_en [1:NUMPADS];// Slew rate limiter enable.
logic input_val [1:NUMPADS];// Digital input value.
// - PADS Analog Interface -
logic ana_override [1:NUMPADS];// Disables digital output when driving analog output.
wire ana [1:NUMPADS];
// ***************************************************************************
// Modports
// ***************************************************************************
modport mp_pads(
input pullup_en,
input pulldown_en,
input output_en,
input output_val,
input slew_limit_en,
input input_en,
output input_val,
input ana_override,
inout ana );
modport mp_dig(
import IsPad,
import IsPort,
import Init,
output pullup_en,
output pulldown_en,
output output_en,
output output_val,
output slew_limit_en,
output input_en,
input input_val );
modport mp_ana(
import IsPad,
output ana_override,
inout ana );
// ***************************************************************************
// Check for which pins exists
// ***************************************************************************
bit [PINID_D7:PINID_A0] exists;
function automatic void Init( );
exists = {(PINID_D7+1){1'b0}};
for ( int i = 1; i <= $size( pinout ); i++ )
if ( PINID_D7 >= pinout[i].id )
exists[pinout[i].id] = 1'b1;
endfunction
// ***************************************************************************
// Functions and Tasks
// ***************************************************************************
function automatic bit IsPad( integer i );
IsPad = exists[i];
endfunction
function automatic bit IsPort( integer i );
IsPort = |exists[8*i+:8];
endfunction
endinterface // pads_if

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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
`ifndef _PINOUT_H_SV_
`define _PINOUT_H_SV_
// *****************************************************************************
// Structs/Unions
// *****************************************************************************
// **** Pin Descriptor ****
// - Pin Descriptor -
typedef struct packed
{
t_pinid id;
t_padtype padtype;
int aux;
} t_pin_descriptor;
// *****************************************************************************
// Pinout
// *****************************************************************************
// **** Preferred Solution !!!! ****
localparam t_pin_descriptor
pinout[ 1: 6]
= '{
'{default:0, id:PINID_A0, padtype:PADTYPE_GPIO, aux:1},
'{default:0, id:PINID_A1, padtype:PADTYPE_GPIO},
'{default:0, id:PINID_A2, padtype:PADTYPE_GPIO},
'{default:0, id:PINID_D0, padtype:PADTYPE_GPIO},
'{default:0, id:PINID_VDD0, padtype:PADTYPE_VDD},
'{default:0, id:PINID_GND0, padtype:PADTYPE_GND}
};
// **** Workaround !!!! ****
typedef enum int
{
pinout_wa_id = 1,
pinout_wa_padtype,
pinout_wa_aux
} t_pinout_wa;
localparam int pinout_size = 6;
localparam int pinout_wa[1:pinout_size][pinout_wa_id:pinout_wa_aux] =
'{
'{PINID_A0, PADTYPE_GPIO, 0},
'{PINID_A1, PADTYPE_GPIO, 0},
'{PINID_A2, PADTYPE_GPIO, 0},
'{PINID_D0, PADTYPE_GPIO, 0},
'{PINID_VDD0, PADTYPE_VDD, 0},
'{PINID_GND0, PADTYPE_GND , 0}
};
`endif // `ifndef _PINOUT_H_SV_
// **** End of File ****

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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
module ports
#( parameter
ID = 1 )
(
// ***************************************************************************
// Module Interface (interfaces, outputs, and inputs)
// ***************************************************************************
genbus_if.slave dbus,
pads_if.mp_dig padsif,
// - System -
input logic clk,
input logic rst
);
// ***************************************************************************
// Regs and Wires
// ***************************************************************************
// **** Internal Data Bus ****
logic [15:0] sdata;
logic ws;
logic [15:0] mdata;
logic [15:0] adr;
logic [1:0] we;
logic [1:0] re;
// **** Interal Registers ****
struct
{
logic [7:0][1:0] in;
logic [7:0] dir;
logic [7:0] out;
struct
{
logic [7:2] reserved;
logic pullupen;
logic slewlim;
} cfg;
} port [PORTID_A:PORTID_D];
// ***************************************************************************
// "dbus" Connection
// ***************************************************************************
always_comb
begin: dbus_Connect
dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr), .we(we), .re(re) );
end
// ***************************************************************************
// Register Access
// For PORTA...PORTD (Excluding I and O)
// +0x00 DIR
// +0x01 OUT
// +0x02 IN
// +0x03 CFG
// ***************************************************************************
always_comb begin padsif.Init(); end
// **** Register Write ****
always_ff @( posedge clk )
begin
// - Local Variables -
integer i, j;
// **** Setup Port Registers ****
for ( j = PORTID_A; j <= PORTID_D; j++ )
begin
if ( padsif.IsPort( j ) )
begin
if ( ((adr[3:2] == j[1:0]) && (adr[1] == 1'b0)) | rst )
begin
if ( we[0] )
port[j].dir <= mdata[7:0];
if ( we[1] )
port[j].out <= mdata[15:8];
end
end
else
begin
port[j].dir <= 8'h00;
port[j].out <= 8'h00;
end
end
end
// **** Regiser Read ****
always_comb
begin: RegisterRead
// - Local Variables -
integer i, j;
logic [7:0] data [PORTID_D:PORTID_A][3:0];
// **** Output to "dbus" ****
// - Setup read multiplexer -
for ( j = PORTID_A; j <= PORTID_D; j++ )
begin
if ( padsif.IsPort( j ) )
data[j] = '{ port[j].dir, port[j].out, 8'h00, 8'h00 };
else
data[j] = '{ 8'h00, 8'h00, 8'h00, 8'h00 };
end
// - Connect "genbusif" -
sdata = { 8'h00, data[ adr[3:2] ][ adr[1:0] ] };
ws = 1'b0;
end
// ***************************************************************************
// Output
// ***************************************************************************
always_comb
begin
// - Local Variables -
integer i, j;
// **** Defaults ****
for ( i = 1; i <= $size( pinout ); i++ )
begin
padsif.pullup_en [i] = 1'b0;
padsif.pulldown_en [i] = 1'b0;
padsif.output_en [i] = 1'b0;
padsif.output_val [i] = 1'b0;
padsif.slew_limit_en[i] = 1'b0;
padsif.input_en [i] = 1'b0;
end
// **** Connect to Pads ****
for ( i = 1; i <= $size( pinout ); i++ )
begin
j = pinout[i].id;
if ( PINID_D7 >= j )
begin
padsif.output_en [i] = port[j[4:3]].dir[j[2:0]];
padsif.output_val[i] = port[j[4:3]].out[j[2:0]];
end
end
end
endmodule // ports

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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
`ifndef _PORTS_H_SV_
`define _PORTS_H_SV_
// *****************************************************************************
//
// *****************************************************************************
// !!!! Incomplete!
localparam int str_pinid [0:15] =
'{
"DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR",
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7"
};
// **** Port Identifiers ****
typedef enum int
{
PORTID_A = 32'd0, // MUST BE ZERO!
PORTID_B,
PORTID_C,
PORTID_D,
PORTID_E,
PORTID_F,
PORTID_G,
PORTID_H,
// PORTID_I, -> DO NOT USE!
PORTID_J,
PORTID_K,
PORTID_L,
PORTID_M,
PORTID_N,
// PORTID_O, -> DO NOT USE!
PORTID_P,
PORTID_Q,
PORTID_R
} t_portid;
`endif // !`ifdef _PORTS_H_SV_
// **** End of File ****

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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
`ifndef _PROGRAM_H_V_
`define _PROGRAM_H_V_
// *****************************************************************************
// Assembly Mnemonic Defines
// *****************************************************************************
typedef enum reg [3:0] { R0,R1,R2,R3,R4,R5,R6,R7,
R8,R9,R10,R11,R12,R13,R14,R15 } cpu_registers;
`define NOP 16'h0000,
`define JMP( k8 ) {4'h1, 4'h0, 8'h k8},
`define LDI( rd, k8 ) {4'h4, rd, 8'h k8},
`define STS( k8, rs ) {4'h8, rs, 8'h k8},
`define LDS( rd, k8 ) {4'h9, rd, 8'h k8},
`define EOP 16'h0000
// *****************************************************************************
// Include ROM
// *****************************************************************************
`include "rom.sv"
`endif // !`ifdef _PROGRAM_H_V_

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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
// *****************************************************************************
// Code ROM
//
// IMPORTANT!
// Array size must be uppdated according to program size.
// *****************************************************************************
const
logic [15:0] rom[0:13]
= '{
`LDI( R0, 11 )
`LDI( R1, 22 )
`LDI( R2, 33 )
`LDI( R3, 44 )
`STS( 0, R0 )
`STS( 1, R1 )
`STS( 2, R2 )
`STS( 3, R3 )
`LDS( R4, 0 )
`LDS( R5, 1 )
`LDS( R6, 0 )
`LDS( R7, 0 )
`JMP( 00 )
`EOP // End of Program (NOP)
};

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// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// Contributed by M W Lund, Atmel Corporation.
// **** Set simulation time scale ****
`timescale 1ns/1ps