Fix enum name off-by-one, bug854.

src/V3Width.cpp

@@ -1421,14 +1421,12 @@ private:
 		// a map for when the value is many bits and sparse.
 		uint64_t max = 0;
 		{
-		    AstEnumItem* itemp = adtypep->itemsp();
-		    while (itemp && itemp->nextp()) {
-			itemp = itemp->nextp()->castEnumItem();
+		    for (AstEnumItem* itemp = adtypep->itemsp(); itemp; itemp = itemp->nextp()->castEnumItem()) {
 			AstConst* vconstp = itemp->valuep()->castConst();
 			if (!vconstp) nodep->v3fatalSrc("Enum item without constified value");
 			if (vconstp->toUQuad() >= max) max = vconstp->toUQuad();
 		    }
-		    if (itemp->width() > 64 || max >= 1024) {
+		    if (adtypep->itemsp()->width() > 64 || max >= 1024) {
 			nodep->v3error("Unsupported; enum next/prev method on enum with > 10 bits");
 			return;
 		    }
@@ -3312,6 +3310,7 @@ private:
 	if (pos != m_tableMap.end()) {
 	    return pos->second;
 	}
+	UINFO(9, "Construct Venumtab attr="<<attrType.ascii()<<" max="<<maxdim<<" for "<<nodep<<endl);
 	AstNodeDType* basep;
 	if (attrType == AstAttrType::ENUM_NAME) {
 	    basep = nodep->findStringDType();
@@ -3335,8 +3334,10 @@ private:
 	// Find valid values and populate
 	if (!nodep->itemsp()) nodep->v3fatalSrc("enum without items");
 	vector<AstNode*> values;
-	values.reserve(maxdim);
-	for (unsigned i=0; i<(maxdim+1); ++i) values[i] = NULL;
+	values.reserve(maxdim+1);
+	for (unsigned i=0; i<(maxdim+1); ++i) {
+	    values[i] = NULL;
+	}
 	{
 	    AstEnumItem* firstp = nodep->itemsp();
 	    AstEnumItem* prevp = firstp; // Prev must start with last item

test_regress/t/t_enum_name2.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_enum_name2.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Jonathon Donaldson.
+
+package our_pkg;
+   typedef enum logic [8-1:0] {
+			       ADC_IN2IN = 8'h99,
+			       ADC_IMMED = 8'h88,
+			       ADC_INDIR = 8'h86,
+			       ADC_INIDX = 8'h97
+			       } T_Opcode;
+endpackage : our_pkg
+
+module t ();
+   our our ();
+endmodule
+
+module our
+  import our_pkg::*;
+   ();
+
+   T_Opcode IR = ADC_IN2IN;
+
+   initial begin
+      $write ("%s (%t)\n", IR.name, $realtime);
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule