Commentary
This commit is contained in:
parent
b7c2c83c88
commit
8cf12416c0
|
|
@ -2985,6 +2985,11 @@ One limit is that you cannot under either license release a commercial
|
||||||
Verilog simulation product incorporating Verilator without making the
|
Verilog simulation product incorporating Verilator without making the
|
||||||
source code available.
|
source code available.
|
||||||
|
|
||||||
|
As is standard with Open Source, contributions back to Verilator will be
|
||||||
|
placed under the Verilator copyright and LGPL/Artistic license. Small test
|
||||||
|
cases will be released into the public domain so they can be used anywhere,
|
||||||
|
large tests under the LGPL/Artistic, unless requested otherwise.
|
||||||
|
|
||||||
=item Why is Verilation so slow?
|
=item Why is Verilation so slow?
|
||||||
|
|
||||||
Verilator needs more memory than the resulting simulator will require, as
|
Verilator needs more memory than the resulting simulator will require, as
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue