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Fix loosing logic/bit difference and -x-initial-edge fallout, bug604. 

Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
This commit is contained in:
Jeremy Bennett 2013-01-17 07:16:19 -05:00 committed by Wilson Snyder
parent 6d1b42bedb
commit 8b47c4e307
3 changed files with 12 additions and 15 deletions
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4
src/V3AstNodes.cpp
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@ -543,9 +543,7 @@ AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, AstBasicDTypeKwd kw
LogicMap::const_iterator it = mapr.find(widths); LogicMap::const_iterator it = mapr.find(widths);
if (it != mapr.end()) return it->second; if (it != mapr.end()) return it->second;
// //
AstBasicDType* new1p = new AstBasicDType(fl, AstBasicDTypeKwd::BIT, numeric, width, widthMin); AstBasicDType* new1p = new AstBasicDType(fl, kwd, numeric, width, widthMin);
// Above should be below, but fails --x-initial-edge test
//AstBasicDType* new1p = new AstBasicDType(fl, kwd, numeric, width, widthMin);
// Because the detailed map doesn't update this map, // Because the detailed map doesn't update this map,
// check the detailed map for this same node, and if found update this map // check the detailed map for this same node, and if found update this map
// Also adds this new node to the detailed map // Also adds this new node to the detailed map

21
src/V3EmitC.cpp
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@ -1368,17 +1368,16 @@ void EmitCImp::emitVarResets(AstNodeModule* modp) {
} else { } else {
puts(varp->name()); puts(varp->name());
for (int v=0; v<vects; ++v) puts( "[__Vi"+cvtToStr(v)+"]"); for (int v=0; v<vects; ++v) puts( "[__Vi"+cvtToStr(v)+"]");
if (zeroit) { // If --x-initial-edge is set, we want to force an initial
// We want to force an initial edge on uninitialized clocks (from 'X' to // edge on uninitialized clocks (from 'X' to whatever the
// whatever the first value is). Since the class is instantiated before // first value is). Since the class is instantiated before
// initial blocks are evaluated, this should not clash with any initial // initial blocks are evaluated, this should not clash
// block settings. Clocks are always BIT datatypes, so zeroit is true. // with any initial block settings.
if (v3Global.opt.xInitialEdge() if (zeroit || (v3Global.opt.xInitialEdge() && varp->isUsedClock())) {
&& (0 == varp->name().find("__Vclklast__"))) { puts(" = 0;\n");
puts(" = 1;\n"); } else if (v3Global.opt.xInitialEdge()
} else { && (0 == varp->name().find("__Vclklast__"))) {
puts(" = 0;\n"); puts(" = 1;\n");
}
} else { } else {
puts(" = VL_RAND_RESET_"); puts(" = VL_RAND_RESET_");
emitIQW(varp); emitIQW(varp);

2
test_regress/t/t_cover_toggle.pl
View File

@ -18,7 +18,7 @@ execute (
# Read the input .v file and do any CHECK_COVER requests # Read the input .v file and do any CHECK_COVER requests
inline_checks(); inline_checks();
file_grep ($Self->{stats}, qr/Coverage, Toggle points joined\s+(\d+)/i, 24) file_grep ($Self->{stats}, qr/Coverage, Toggle points joined\s+(\d+)/i, 25)
if $Self->{vlt}; if $Self->{vlt};
ok(1); ok(1);