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Fix loosing logic/bit difference and -x-initial-edge fallout, bug604.

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Signed-off-by: Wilson Snyder <[email protected]>
This commit is contained in:
Jeremy Bennett
2013-01-17 07:16:19 -05:00
committed by Wilson Snyder
parent 6d1b42bedb
commit 8b47c4e307
3 changed files with 12 additions and 15 deletions
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src/V3EmitC.cpp
+10 -11
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@@ -1368,17 +1368,16 @@ void EmitCImp::emitVarResets(AstNodeModule* modp) {
} else {
puts(varp->name());
for (int v=0; v<vects; ++v) puts( "[__Vi"+cvtToStr(v)+"]");
if (zeroit) {
// We want to force an initial edge on uninitialized clocks (from 'X' to
// whatever the first value is). Since the class is instantiated before
// initial blocks are evaluated, this should not clash with any initial
// block settings. Clocks are always BIT datatypes, so zeroit is true.
if (v3Global.opt.xInitialEdge()
&& (0 == varp->name().find("__Vclklast__"))) {
puts(" = 1;\n");
} else {
puts(" = 0;\n");
}
// If --x-initial-edge is set, we want to force an initial
// edge on uninitialized clocks (from 'X' to whatever the
// first value is). Since the class is instantiated before
// initial blocks are evaluated, this should not clash
// with any initial block settings.
if (zeroit || (v3Global.opt.xInitialEdge() && varp->isUsedClock())) {
puts(" = 0;\n");
} else if (v3Global.opt.xInitialEdge()
&& (0 == varp->name().find("__Vclklast__"))) {
puts(" = 1;\n");
} else {
puts(" = VL_RAND_RESET_");
emitIQW(varp);