Tests: skip test for bug462

src/V3Tristate.cpp

@@ -656,6 +656,18 @@ private:
     virtual void visit(AstVar* nodep, AstNUser*) {
 	if (m_state == CONVERT_VARS) {
 	    if (nodep->isTristate() && !m_ftaskp) {
+		// Add pullups/pulldowns so next stage can ignore wire type
+		// See test_regress/t/t_tri_pull01.v test, it fails for other reasons
+		//if (nodep->varType() == AstVarType::TRIWIRE0) {
+		//    nodep->addNext(new AstPull(nodep->fileline(),
+		//			       new AstVarRef(nodep->fileline(), nodep, true),
+		//			       false));
+		//}
+		//if (nodep->varType() == AstVarType::TRIWIRE1) {
+		//    nodep->addNext(new AstPull(nodep->fileline(),
+		//			       new AstVarRef(nodep->fileline(), nodep, true),
+		//			       true));
+		//}
 		// create the input var and leave the original as the output var
 		AstVar* varinp = nodep->cloneTree(false)->castVar();
 		varinp->name(varinp->name() + "__in");

test_regress/t/t_tri_pull01.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->skip("Verilator unsupported, bug462");
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_tri_pull01.v

@@ -0,0 +1,60 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Test:
+   tri 	t;
+   bufif1 (t, crc[1], cyc[1:0]==2'b00);
+   bufif1 (t, crc[2], cyc[1:0]==2'b10);
+
+   tri0 t0;
+   bufif1 (t0, crc[1], cyc[1:0]==2'b00);
+   bufif1 (t0, crc[2], cyc[1:0]==2'b10);
+
+   tri1 t1;
+   bufif1 (t1, crc[1], cyc[1:0]==2'b00);
+   bufif1 (t1, crc[2], cyc[1:0]==2'b10);
+
+   wire [63:0] 	result = {59'h0, t1, 3'h0, t0};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h14f90df4eab2c499
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule