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Correctly compute witdh of AstReplicate in its constructor when the count is unsigned but its MSB is set.
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+3
-2
@@ -3367,8 +3367,9 @@ public:
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: ASTGEN_SUPER_Replicate(fl, lhsp, rhsp) {
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: ASTGEN_SUPER_Replicate(fl, lhsp, rhsp) {
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if (lhsp) {
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if (lhsp) {
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if (const AstConst* const constp = VN_CAST(rhsp, Const)) {
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if (const AstConst* const constp = VN_CAST(rhsp, Const)) {
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if (constp->num().isFourState() || constp->num().isNegative()) { // V3Width warns
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if (constp->num().isFourState()
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dtypeSetLogicSized(lhsp->width(), VSigning::UNSIGNED);
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|| (constp->dtypep()->isSigned() && constp->num().isNegative())) {
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dtypeSetLogicSized(lhsp->width(), VSigning::UNSIGNED); // V3Width warns
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} else {
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} else {
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dtypeSetLogicSized(lhsp->width() * constp->toSInt(), VSigning::UNSIGNED);
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dtypeSetLogicSized(lhsp->width() * constp->toSInt(), VSigning::UNSIGNED);
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}
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}
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@@ -243,6 +243,10 @@ module t (
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assign ascending_assign[4:7] = arand_b[0:3];
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assign ascending_assign[4:7] = arand_b[0:3];
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`signal(ASCENDING_ASSIGN, ascending_assign);
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`signal(ASCENDING_ASSIGN, ascending_assign);
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// Special cases to be covered
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`signal(REPLICATE_WIDTH, {4'd8{rand_a[0]}}); // Replicate count unsigned, but MSB set
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if ($bits(REPLICATE_WIDTH) != 8) $fatal("%0d != 8", $bits(REPLICATE_WIDTH));
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// Sel from not requires the operand to have a sinle sink, so can't use
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// Sel from not requires the operand to have a sinle sink, so can't use
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// the chekc due to the raw expression referencing the operand
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// the chekc due to the raw expression referencing the operand
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wire [63:0] sel_from_not_tmp = ~(rand_a >> rand_b[2:0] << rand_a[3:0]);
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wire [63:0] sel_from_not_tmp = ~(rand_a >> rand_b[2:0] << rand_a[3:0]);
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