Tests: Add force/release tests.

test_regress/t/t_force.out

@@ -0,0 +1,26 @@
+%Error-UNSUPPORTED: t/t_force.v:25:7: Unsupported: Verilog 1995 force
+   25 |       force bus[1:0] = 2'b10;
+      |       ^~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_force.v:29:7: Unsupported: Verilog 1995 release
+   29 |       release bus;
+      |       ^~~~~~~
+%Error-UNSUPPORTED: t/t_force.v:43:10: Unsupported: Verilog 1995 force
+   43 |          force never_driven = 32'h888;
+      |          ^~~~~
+%Error-UNSUPPORTED: t/t_force.v:56:10: Unsupported: Verilog 1995 release
+   56 |          release never_forced;   
+      |          ^~~~~~~
+%Error-UNSUPPORTED: t/t_force.v:65:10: Unsupported: Verilog 1995 force
+   65 |          force bus = 4'b0111;
+      |          ^~~~~
+%Error-UNSUPPORTED: t/t_force.v:69:10: Unsupported: Verilog 1995 force
+   69 |          force bus = 4'b1111;
+      |          ^~~~~
+%Error-UNSUPPORTED: t/t_force.v:73:10: Unsupported: Verilog 1995 release
+   73 |          release bus;
+      |          ^~~~~~~
+%Error-UNSUPPORTED: t/t_force.v:85:10: Unsupported: Verilog 1995 release
+   85 |          release bus[0];
+      |          ^~~~~~~
+%Error: Exiting due to

test_regress/t/t_force.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2021 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;

test_regress/t/t_force.v

@@ -0,0 +1,102 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc = 0;
+
+   reg [3:0]  in;
+   tri [3:0]  bus = in;
+
+   int        never_driven;
+   int        never_forced;
+
+   task force_bus;
+      force bus[1:0] = 2'b10;
+   endtask
+
+   task release_bus;
+      release bus;
+   endtask
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 0) begin
+         in <= 4'b0101;
+      end
+      else if (cyc == 1) begin
+         `checkh(in, 4'b0101);
+      end
+      // Check forces with no driver
+      if (cyc == 1) begin
+         force never_driven = 32'h888;
+      end
+      else if (cyc == 2) begin
+         `checkh(never_driven, 32'h888);
+      end
+      // Check release with no force
+      else if (cyc == 10) begin
+         never_forced <= 5432;
+      end
+      else if (cyc == 11) begin
+         `checkh(never_forced, 5432);
+      end
+      else if (cyc == 12) begin
+         release never_forced;  // no-op
+      end
+      else if (cyc == 13) begin
+         `checkh(never_forced, 5432);
+      end
+      //
+      // bus
+      else if (cyc == 10) begin
+         `checkh(bus, 4'b0101);
+         force bus = 4'b0111;
+      end
+      else if (cyc == 11) begin
+         `checkh(bus, 4'b0111);
+         force bus = 4'b1111;
+      end
+      else if (cyc == 12) begin
+         `checkh(bus, 4'b1111);
+         release bus;
+      end
+      else if (cyc == 13) begin
+         `checkh(bus, 4'b0101);
+      end
+      else if (cyc == 20) begin
+         force_bus();
+      end
+      else if (cyc == 21) begin
+         `checkh(bus, 4'b0110);
+      end
+      else if (cyc == 22) begin
+         release bus[0];
+      end
+      else if (cyc == 23) begin
+         `checkh(bus, 4'b0111);
+         release_bus();
+      end
+      else if (cyc == 24) begin
+         `checkh(in, 4'b0101);
+         `checkh(bus, 4'b0101);
+      end
+      //
+      else if (cyc == 99) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule

test_regress/t/t_force_mid.out

@@ -0,0 +1,5 @@
+%Error-UNSUPPORTED: t/t_force_mid.v:29:10: Unsupported: Verilog 1995 force
+   29 |          force tried = 4'b1010;
+      |          ^~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

test_regress/t/t_force_mid.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;

test_regress/t/t_force_mid.v

@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+
+module t(/*AUTOARG*/
+   // Inouts
+   tried,
+   // Inputs
+   clk
+   );
+   input clk;
+   inout tri [3:0] tried;
+
+   integer cyc = 0;
+
+   assign tried = 4'b0101;
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 0) begin
+         if (tried != 4'b0101) $stop;
+      end
+      else if (cyc == 1) begin
+         force tried = 4'b1010;
+      end
+      else if (cyc == 2) begin
+         if (tried != 4'b1010) $stop;
+      end
+      //
+      else if (cyc == 99) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule

test_regress/t/t_force_subnet.out

@@ -0,0 +1,11 @@
+%Error-UNSUPPORTED: t/t_force_subnet.v:27:10: Unsupported: Verilog 1995 force
+   27 |          force sub1.subnet = 8'h00;   
+      |          ^~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_force_subnet.v:31:10: Unsupported: Verilog 1995 force
+   31 |          force subnet = 8'h10;   
+      |          ^~~~~
+%Error-UNSUPPORTED: t/t_force_subnet.v:35:10: Unsupported: Verilog 1995 release
+   35 |          release subnet;   
+      |          ^~~~~~~
+%Error: Exiting due to

test_regress/t/t_force_subnet.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2021 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;

test_regress/t/t_force_subnet.v

@@ -0,0 +1,56 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc = 0;
+
+   tri        logic [7:0] subnet;
+   sub1 sub1(.*);
+   sub2 sub2(.*);
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 10) begin
+         `checkh(subnet, 8'h11);
+         force sub1.subnet = 8'h00;  // sub1.subnet same as subnet
+      end
+      else if (cyc == 11) begin
+         `checkh(subnet, 8'h00);
+         force subnet = 8'h10;  // sub1.subnet same as subnet
+      end
+      else if (cyc == 12) begin
+         `checkh(subnet, 8'h10);
+         release subnet;  // sub1.subnet same as subnet
+      end
+      else if (cyc == 13) begin
+         `checkh(subnet, 8'h11);
+      end
+      //
+      else if (cyc == 99) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+module sub1(inout logic [7:0] subnet);
+   assign subnet = 8'hz1;
+endmodule
+
+module sub2(inout logic [7:0] subnet);
+   assign subnet = 8'h1z;
+endmodule
+

test_regress/t/t_force_subvar.out

@@ -0,0 +1,8 @@
+%Error-UNSUPPORTED: t/t_force_subvar.v:26:10: Unsupported: Verilog 1995 force
+   26 |          force sub.subvar = 32'hffff;
+      |          ^~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_force_subvar.v:36:10: Unsupported: Verilog 1995 release
+   36 |          release sub.subvar;
+      |          ^~~~~~~
+%Error: Exiting due to

test_regress/t/t_force_subvar.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2021 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;

test_regress/t/t_force_subvar.v

@@ -0,0 +1,57 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc = 0;
+
+   sub sub();
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      // procedural var sub.subvar
+      if (cyc == 50) begin
+         `checkh(sub.subvar, 32'h666);
+         force sub.subvar = 32'hffff;
+      end
+      else if (cyc == 51) begin
+         `checkh(sub.subvar, 32'hffff);
+         sub.subvar = 32'h543;  // Ignored as still forced
+      end
+      else if (cyc == 52) begin
+         `checkh(sub.subvar, 32'hffff);
+      end
+      else if (cyc == 53) begin
+         release sub.subvar;
+      end
+      else if (cyc == 54) begin
+         `checkh(sub.subvar, 32'hffff);  // Retains value until next procedural change
+         sub.subvar = 32'h544;
+      end
+      else if (cyc == 56) begin
+         `checkh(sub.subvar, 32'h544);
+      end
+      //
+      else if (cyc == 99) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+module sub;
+   int subvar;
+   initial subvar = 32'h666;
+endmodule

test_regress/t/t_force_tri.out

@@ -0,0 +1,5 @@
+%Error-UNSUPPORTED: t/t_force_tri.v:27:10: Unsupported: Verilog 1995 force
+   27 |          force bus = 4'bzz10;
+      |          ^~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

test_regress/t/t_force_tri.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;

test_regress/t/t_force_tri.v

@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc = 0;
+
+   logic [3:0] bus;
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 0) begin
+         bus <= 4'b0101;
+      end
+      else if (cyc == 1) begin
+         force bus = 4'bzz10;
+      end
+      else if (cyc == 2) begin
+         `checkh(bus, 4'bzz10);
+      end
+      //
+      else if (cyc == 99) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule

test_regress/t/t_tri_dangle.v

@@ -29,4 +29,6 @@ module sub (/*AUTOARG*/
    // verilator no_inline_module
    inout AVDD;
    inout AVSS;
+   tri NON_IO;
+   initial if (NON_IO !== 'z) $stop;
 endmodule