Internals: Add -fno-dead-cells, -fno-dead-assigns for debug use

src/V3Dead.cpp

@@ -291,7 +291,7 @@ class DeadVisitor final : public VNVisitor {
             checkAll(nodep);
             // Has to be direct assignment without any EXTRACTing.
             AstVarRef* const varrefp = VN_CAST(nodep->lhsp(), VarRef);
-            if (varrefp && !m_sideEffect
+            if (varrefp && !m_sideEffect && v3Global.opt.fDeadAssigns()
                 && varrefp->varScopep()) {  // For simplicity, we only remove post-scoping
                 m_assignMap.emplace(varrefp->varScopep(), nodep);
                 checkAll(varrefp);  // Must track reference to dtype()
@@ -387,7 +387,7 @@ class DeadVisitor final : public VNVisitor {
 
     void deadCheckCells() {
         for (AstCell* cellp : m_cellsp) {
-            if (cellp->user1() == 0 && !cellp->modp()->stmtsp()) {
+            if (cellp->user1() == 0 && !cellp->modp()->stmtsp() && v3Global.opt.fDeadCells()) {
                 cellp->modp()->user1Inc(-1);
                 deleting(cellp);
             }

src/V3Options.cpp

@@ -1215,6 +1215,8 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
     });
     DECL_OPTION("-fdfg-pre-inline", FOnOff, &m_fDfgPreInline);
     DECL_OPTION("-fdfg-post-inline", FOnOff, &m_fDfgPostInline);
+    DECL_OPTION("-fdead-assigns", FOnOff, &m_fDeadAssigns);
+    DECL_OPTION("-fdead-cells", FOnOff, &m_fDeadCells);
     DECL_OPTION("-fexpand", FOnOff, &m_fExpand);
     DECL_OPTION("-fgate", FOnOff, &m_fGate);
     DECL_OPTION("-finline", FOnOff, &m_fInline);
@@ -1953,6 +1955,8 @@ void V3Options::optimize(int level) {
     m_fDedupe = flag;
     m_fDfgPreInline = flag;
     m_fDfgPostInline = flag;
+    m_fDeadAssigns = flag;
+    m_fDeadCells = flag;
     m_fExpand = flag;
     m_fGate = flag;
     m_fInline = flag;

src/V3Options.h

@@ -363,6 +363,8 @@ private:
     bool m_fDfgPeephole = true; // main switch: -fno-dfg-peephole
     bool m_fDfgPreInline;    // main switch: -fno-dfg-pre-inline and -fno-dfg
     bool m_fDfgPostInline;   // main switch: -fno-dfg-post-inline and -fno-dfg
+    bool m_fDeadAssigns;     // main switch: -fno-dead-assigns: remove dead assigns
+    bool m_fDeadCells;   // main switch: -fno-dead-cells: remove dead cells
     bool m_fExpand;      // main switch: -fno-expand: expansion of C macros
     bool m_fGate;        // main switch: -fno-gate: gate wire elimination
     bool m_fInline;      // main switch: -fno-inline: module inlining
@@ -626,6 +628,8 @@ public:
     bool fDfgPeepholeEnabled(const std::string& name) const {
         return !m_fDfgPeepholeDisabled.count(name);
     }
+    bool fDeadAssigns() const { return m_fDeadAssigns; }
+    bool fDeadCells() const { return m_fDeadCells; }
     bool fExpand() const { return m_fExpand; }
     bool fGate() const { return m_fGate; }
     bool fInline() const { return m_fInline; }

test_regress/t/t_opt_dead_noassigns.pl

@@ -0,0 +1,25 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['--fno-dead-assigns'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}_*.cpp");
+file_grep_any(\@files, qr/keptdead/ix);
+
+ok(1);
+1;

test_regress/t/t_opt_dead_noassigns.v

@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   in
+   );
+   input int in;
+
+   int ass_keptdead;
+
+   initial begin
+      if (in != 0) begin
+         ass_keptdead = 1 | in;
+         $display("Avoid gate removing");
+         ass_keptdead = 2 | in;
+      end
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_opt_dead_nocells.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ['--fno-inline', '--fno-dead-cells'],
+    );
+
+my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}_*.h");
+file_grep_any(\@files, qr/keptdead/ix);
+
+ok(1);
+1;

test_regress/t/t_opt_dead_nocells.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module Mod_Dead;
+endmodule
+
+module t (/*AUTOARG*/);
+
+   Mod_Dead cell_keptdead();
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule