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Fix error with tasks that have output first, bug78.

This commit is contained in:
Wilson Snyder 2009-04-08 14:33:12 -04:00
parent 3d85cbe6b5
commit 86f08a341c
3 changed files with 5 additions and 2 deletions
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2
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@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.7*** * Verilator 3.7***
**** Fix error with tasks that have output first, bug78. [Andrea Foletto]
**** Fix "cloning" error with -y/--top-module, bug76. [Dimitris Nalbantis] **** Fix "cloning" error with -y/--top-module, bug76. [Dimitris Nalbantis]
* Verilator 3.702 2009/03/28 * Verilator 3.702 2009/03/28

1
src/V3Delayed.cpp
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@ -415,6 +415,7 @@ private:
else if (!m_inDly && nodep->lvalue()) { else if (!m_inDly && nodep->lvalue()) {
//UINFO(9,"NBA "<<nodep<<endl); //UINFO(9,"NBA "<<nodep<<endl);
if (!m_inInitial) { if (!m_inInitial) {
UINFO(4,"AssignNDlyVar: "<<nodep<<endl);
markVarUsage(nodep->varp(), VU_NONDLY); markVarUsage(nodep->varp(), VU_NONDLY);
} }
} }

4
src/V3LinkLValue.cpp
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@ -211,10 +211,10 @@ private:
if (AstVar* portp = stmtp->castVar()) { if (AstVar* portp = stmtp->castVar()) {
if (portp->isIO()) { if (portp->isIO()) {
if (portp->isInput()) { if (portp->isInput()) {
pinp->iterateAndNext(*this); pinp->iterate(*this);
} else { // Output or Inout } else { // Output or Inout
m_setRefLvalue = true; m_setRefLvalue = true;
pinp->iterateAndNext(*this); pinp->iterate(*this);
m_setRefLvalue = false; m_setRefLvalue = false;
} }
// Advance pin // Advance pin