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Internals: Move the eval loop into the runtime library (#8225)
The loops modelling the SystemVerilog scheduling regions are no longer generated. They now live in 'VerilatedEvalLoop' in the runtime library. The generated model holds one as a member, passing itself to it, and exposes each evaluation entry point to it as a pure virtual method on VerilatedModel. The model's 'eval' and 'eval_step' remain the top level entry points, and are backward compatible. V3Sched no longer emits '_eval' or '_eval_settle', etc.. Instead every evaluation entry point called from the runtime is enumerated by 'VEval', Scheduling creates all entry points, for all scheduling regions, even if they are empty, and the runtime eval loop calls everything unconditionally. If regions are empty, this is simply a call to an empty function. This will hurt performance on very small models, but should not be noticeable on anything meaningful, so it is likely best to keep to reduce complexity. A scheduling entry points evaluate a single iteration and returns whether it did any work, they are effectively the previous `_eval_phase_*` functions.
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+4
-14
@@ -63,7 +63,7 @@ class ClockVisitor final : public VNVisitor {
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// NODE STATE
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// STATE
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AstCFunc* m_sampleCFuncp = nullptr; // The CFunc to populate with sampled value assignments
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AstCFunc* const m_sampleCFuncp; // The CFunc to populate with sampled value assignments
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// VISITORS
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void visit(AstCoverToggle* nodep) override {
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@@ -106,11 +106,6 @@ class ClockVisitor final : public VNVisitor {
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if (!varp->valuep()) return;
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if (!varp->sampled()) return;
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// Create the containing function on first encounter
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if (!m_sampleCFuncp) {
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m_sampleCFuncp = V3Sched::util::makeSubFunction(v3Global.rootp(), "_sample", false);
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}
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FileLine* const flp = nodep->fileline();
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AstNodeExpr* const rhsp = VN_AS(varp->valuep()->unlinkFrBack(), NodeExpr);
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AstVarRef* const lhsp = new AstVarRef{flp, nodep, VAccess::WRITE};
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@@ -124,15 +119,10 @@ class ClockVisitor final : public VNVisitor {
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public:
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// CONSTRUCTORS
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explicit ClockVisitor(AstNetlist* netlistp) {
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explicit ClockVisitor(AstNetlist* netlistp)
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: m_sampleCFuncp{netlistp->evalFuncp(VEval::SAMPLE)} {
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iterate(netlistp);
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// If we need a sample function, call it at the begining of eval
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if (m_sampleCFuncp) {
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V3Sched::util::splitCheck(m_sampleCFuncp);
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AstCCall* const callp = new AstCCall{m_sampleCFuncp->fileline(), m_sampleCFuncp};
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callp->dtypeSetVoid();
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netlistp->evalp()->stmtsp()->addHereThisAsNext(callp->makeStmt());
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}
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V3Sched::util::splitCheck(m_sampleCFuncp);
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}
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~ClockVisitor() override = default;
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};
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