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Ignore --x-initial unique inside classes.

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Wilson Snyder
2022-01-02 12:26:10 -05:00
parent b7ad1e6d61
commit 84ee833ea7
2 changed files with 10 additions and 4 deletions
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docs/guide/exe_verilator.rst
+4 -3
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@@ -1364,9 +1364,10 @@ Summary:
.. note::
This option applies only to values which are explicitly written as X
in the Verilog source code. Initial values of clocks are set to 0
unless `--x-initial-edge` is specified. Initial values of all other
state holding variables are controlled with `--x-initial`.
in modules (not classes) in the Verilog source code. Initial values
of clocks are set to 0 unless `--x-initial-edge` is
specified. Initial values of all other state holding variables are
controlled with `--x-initial`.
.. option:: --x-initial 0