Test added

test_regress/t/t_inst_misarray_bad.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug595");
+
+compile (
+	 verilator_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+'TBD
+%Error: Exiting due to.*',
+	 );
+
+
+ok(1);
+1;

test_regress/t/t_inst_misarray_bad.v

@@ -0,0 +1,40 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   logic foo; initial foo = 0;
+
+//   dut #(.W(4)) udut(.*);
+   dut #(.W(4)) udut(.clk(clk),
+		     .foo(foo));  // Should be a non-internal error, as assigning logic to logic array
+
+endmodule
+
+module dut
+    #(parameter W = 1)
+    (input logic clk,
+     input logic foo[W-1:0]);
+
+    genvar i;
+    generate
+       for (i = 0; i < W; i++) begin
+          suba ua(.clk(clk), .foo(foo[i]));
+       end
+    endgenerate
+endmodule
+
+module suba
+  (input logic clk,
+   input logic foo);
+
+   always @(posedge clk)
+     $display("foo=%b", foo);
+
+endmodule