Fix gate lvalue optimization error, bug831.

Changes

@@ -22,6 +22,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Support $value$plusargs float and shorts, bug1592, bug1619. [Garrett Smith]
 
+****  Fix gate lvalue optimization error, bug831. [Jonathon Donaldson, Driss Halfdi]
+
 ****  Fix color assertion on empty if, bug1604. [Andrew Holme]
 
 ****  Fix for loop missing initializer, bug1605. [Andrew Holme]

src/V3Gate.cpp

@@ -176,7 +176,7 @@ public:
     virtual ~GateLogicVertex() {}
     // ACCESSORS
     virtual string name() const { return (cvtToHex(m_nodep)+"@"+scopep()->prettyName()); }
-    virtual string dotColor() const { return "yellow"; }
+    virtual string dotColor() const { return "purple"; }
     virtual FileLine* fileline() const { return nodep()->fileline(); }
     AstNode* nodep() const { return m_nodep; }
     AstActive* activep() const { return m_activep; }
@@ -1191,10 +1191,18 @@ private:
                         GateLogicVertex* consumeVertexp
                             = dynamic_cast<GateLogicVertex*>(outedgep->top());
                         AstNode* consumerp = consumeVertexp->nodep();
-                        GateElimVisitor elimVisitor(consumerp, vvertexp->varScp(), dupVarRefp, &m_varVisitor);
+                        m_graphp->dumpDotFilePrefixed("gate_preelim");
+                        UINFO(9, "elim src vtx"<<lvertexp<<" node "<<lvertexp->nodep()<<endl);
+                        UINFO(9, "elim cons vtx"<<consumeVertexp<<" node "<<consumerp<<endl);
+                        UINFO(9, "elim var vtx "<<vvertexp<<" node "<<vvertexp->varScp()<<endl);
+                        UINFO(9, "replace with "<<dupVarRefp<<endl);
+                        if (lvertexp == consumeVertexp) {
+                            UINFO(9, "skipping as self-recirculates\n");
+                        } else {
+                            GateElimVisitor elimVisitor(consumerp, vvertexp->varScp(), dupVarRefp, &m_varVisitor);
+                        }
                         outedgep = outedgep->relinkFromp(dupVvertexp);
                     }
-
                     // Propagate attributes
                     dupVvertexp->propagateAttrClocksFrom(vvertexp);
                     // Remove inputs links

test_regress/t/t_gate_lvalue_const.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_gate_lvalue_const.v

@@ -0,0 +1,65 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Driss Hafdi.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk, rst
+   );
+
+   input clk;
+   input rst;
+
+   logic [2:0] ctrl_inc_single;
+   logic [2:0] ctrl_inc_double;
+
+   logic [2:0] cnt_single;
+   always_ff @(posedge clk) begin
+      if (rst) begin
+         cnt_single <= '0;
+      end
+      else if (ctrl_inc_single != '0 && cnt_single != '1) begin
+         cnt_single <= cnt_single + 1'd1;
+      end
+   end
+
+   logic [2:0] cnt_double;
+   always_ff @(posedge clk) begin
+      if (rst) begin
+         cnt_double <= '0;
+      end
+      else if (ctrl_inc_double != '0 && cnt_double != '1) begin
+         cnt_double <= cnt_double + 1'd1;
+      end
+   end
+
+   always_comb ctrl_inc_single = '0;
+   always_comb ctrl_inc_double = '0;
+
+   testMod test_i (.data_i(cnt_single));
+   testMod test_j (.data_i(cnt_double));
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+module testMod
+   (input wire [2:0] data_i);
+
+   typedef logic [63:0]    time_t;
+   time_t [2:0] last_transition;
+   genvar b;
+
+   generate
+      for (b = 0; b <= 2; b++) begin : gen_trans
+         always_ff @(posedge data_i[b] or negedge data_i[b]) begin
+            last_transition[b] <= $time;
+         end
+      end
+   endgenerate
+
+endmodule