Tests: Cleanup t_cover_assert

This commit is contained in:
Wilson Snyder 2026-02-17 08:47:43 -05:00
parent 089672b200
commit 81d1d79585
3 changed files with 39 additions and 52 deletions

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@ -1,17 +1,6 @@
%Warning-PROCASSINIT: t/t_cover_assert.v:13:18: Procedural assignment to declaration with initial value: 'cyc'
%Error-UNSUPPORTED: t/t_cover_assert.v:38:5: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
: ... note: In instance 't'
: ... Location of variable initialization
13 | integer cyc = 0;
| ^
t/t_cover_assert.v:19:7: ... Location of variable process write
: ... Perhaps should initialize instead using a reset in this process
19 | cyc <= cyc + 1;
| ^~~
... For warning description see https://verilator.org/warn/PROCASSINIT?v=latest
... Use "/* verilator lint_off PROCASSINIT */" and lint_on around source to disable this message.
%Error-UNSUPPORTED: t/t_cover_assert.v:39:11: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
: ... note: In instance 't'
39 | C1: cover property(a)
38 | cover property (a) begin
| ^~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

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@ -4,13 +4,11 @@
// SPDX-FileCopyrightText: 2023 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
integer cyc = 0;
int cyc;
bit a;
bit b;
@ -36,8 +34,8 @@ module t(/*AUTOARG*/
end
always_ff @(posedge clk) begin
C1: cover property(a)
begin
C1 :
cover property (a) begin
// Assert under cover legal in some other simulators
A2 : assert (b);
end

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@ -9,9 +9,9 @@
import vltest_bootstrap
test.scenarios("simulator")
test.scenarios("linter")
test.compile(
test.lint(
verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME --unused-regexp blargh"],
fails=True,
expect_filename=test.golden_filename,