Tests: Cleanup t_cover_assert

test_regress/t/t_cover_assert.out

@@ -1,17 +1,6 @@
-%Warning-PROCASSINIT: t/t_cover_assert.v:13:18: Procedural assignment to declaration with initial value: 'cyc'
+%Error-UNSUPPORTED: t/t_cover_assert.v:38:5: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
-                                              : ... note: In instance 't'
+                                           : ... note: In instance 't'
-                                              : ... Location of variable initialization
+   38 |     cover property (a) begin
-   13 |    integer cyc = 0;
+      |     ^~~~~
-      |                  ^
-                      t/t_cover_assert.v:19:7: ... Location of variable process write
-                                             : ... Perhaps should initialize instead using a reset in this process
-   19 |       cyc <= cyc + 1;
-      |       ^~~
-                      ... For warning description see https://verilator.org/warn/PROCASSINIT?v=latest
-                      ... Use "/* verilator lint_off PROCASSINIT */" and lint_on around source to disable this message.
-%Error-UNSUPPORTED: t/t_cover_assert.v:39:11: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
-                                            : ... note: In instance 't'
-   39 |       C1: cover property(a)
-      |           ^~~~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_cover_assert.v

@@ -4,43 +4,41 @@
 // SPDX-FileCopyrightText: 2023 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-module t(/*AUTOARG*/
+module t (
-   // Inputs
+  input clk
-   clk
+);
-   );
-   input clk;
 
-   integer cyc = 0;
+  int cyc;
-   bit     a;
+  bit a;
-   bit     b;
+  bit b;
 
-   // Test loop
+  // Test loop
-   always @ (posedge clk) begin
+  always @(posedge clk) begin
-      cyc <= cyc + 1;
+    cyc <= cyc + 1;
-      if (cyc == 0) begin
+    if (cyc == 0) begin
-         a <= '0;
+      a <= '0;
-         b <= '0;
+      b <= '0;
-      end
+    end
-      else if (cyc == 10) begin
+    else if (cyc == 10) begin
-         a <= '1;
+      a <= '1;
-         b <= '1;
+      b <= '1;
-      end
+    end
-      else if (cyc == 11) begin
+    else if (cyc == 11) begin
-         a <= '0;
+      a <= '0;
-         b <= '1;
+      b <= '1;
-      end
+    end
-      else if (cyc == 99) begin
+    else if (cyc == 99) begin
-         $write("*-* All Finished *-*\n");
+      $write("*-* All Finished *-*\n");
-         $finish;
+      $finish;
-      end
+    end
-   end
+  end
 
-   always_ff @(posedge clk) begin
+  always_ff @(posedge clk) begin
-      C1: cover property(a)
+    C1 :
-        begin
+    cover property (a) begin
-           // Assert under cover legal in some other simulators
+      // Assert under cover legal in some other simulators
-           A2: assert (b);
+      A2 : assert (b);
-        end
+    end
-   end
+  end
 
 endmodule

test_regress/t/t_lint_unused_func_bad.py

@@ -9,9 +9,9 @@
 
 import vltest_bootstrap
 
-test.scenarios("simulator")
+test.scenarios("linter")
 
-test.compile(
+test.lint(
     verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME --unused-regexp blargh"],
     fails=True,
     expect_filename=test.golden_filename,