Merge a80fe1fe45 into 141fe8bdad
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80b0a94432
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@ -66,6 +66,19 @@ enum ClassRandom : uint8_t {
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static constexpr const char* GLOBAL_CONSTRAINT_SEPARATOR = "__DT__";
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static constexpr const char* BASIC_RANDOMIZE_FUNC_NAME = "__VBasicRand";
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// Walk extends chain to find __Vrandmode variable (stored in AstClass::user2p).
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// user2p is only set on the root class where __Vrandmode was created, so
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// derived classes need this chain walk. Accepts AstNodeModule* for flexibility.
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static AstVar* getRandModeVarFromClass(AstNodeModule* classp) {
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while (classp) {
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if (classp->user2p()) return VN_AS(classp->user2p(), Var);
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AstClass* const cp = VN_CAST(classp, Class);
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if (!cp || !cp->extendsp()) return nullptr;
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classp = cp->extendsp()->classp();
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}
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return nullptr;
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}
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// ######################################################################
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// Establishes the target of a rand_mode() call
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@ -1085,7 +1098,7 @@ class ConstraintExprVisitor final : public VNVisitor {
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AstNodeExpr* randModeAccess;
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if (membersel) {
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AstNodeModule* const varClassp = VN_AS(varp->user2p(), NodeModule);
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AstVar* const effectiveRandModeVarp = VN_AS(varClassp->user2p(), Var);
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AstVar* const effectiveRandModeVarp = getRandModeVarFromClass(varClassp);
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if (effectiveRandModeVarp) {
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// Member's class has randmode, use it
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AstNodeExpr* parentAccess = membersel->fromp()->cloneTree(false);
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@ -1346,7 +1359,7 @@ class ConstraintExprVisitor final : public VNVisitor {
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initTaskp->addStmtsp(methodp->makeStmt());
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if (isGlobalConstrained && membersel && randMode.usesMode) {
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AstNodeModule* const varClassp = VN_AS(varp->user2p(), NodeModule);
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AstVar* const subRandModeVarp = VN_AS(varClassp->user2p(), Var);
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AstVar* const subRandModeVarp = getRandModeVarFromClass(varClassp);
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if (subRandModeVarp) {
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AstNodeExpr* const parentAccess = membersel->fromp()->cloneTree(false);
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AstMemberSel* const randModeSel
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@ -3003,13 +3016,6 @@ class RandomizeVisitor final : public VNVisitor {
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classp->user2p(randModeVarp);
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return randModeVarp;
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}
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static AstVar* getRandModeVar(AstClass* const classp) {
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if (classp->user2p()) return VN_AS(classp->user2p(), Var);
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if (AstClassExtends* const extendsp = classp->extendsp()) {
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return getRandModeVar(extendsp->classp());
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}
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return nullptr;
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}
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AstVar* getCreateConstraintModeVar(AstClass* const classp) {
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if (classp->user4p()) return VN_AS(classp->user4p(), Var);
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if (AstClassExtends* const extendsp = classp->extendsp()) {
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@ -3251,7 +3257,7 @@ class RandomizeVisitor final : public VNVisitor {
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}
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static AstNodeStmt* wrapIfRandMode(AstClass* classp, AstVar* const varp, AstNodeStmt* stmtp) {
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const RandomizeMode rmode = {.asInt = varp->user1()};
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return VN_AS(wrapIfMode(rmode, getRandModeVar(classp), stmtp), NodeStmt);
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return VN_AS(wrapIfMode(rmode, getRandModeVarFromClass(classp), stmtp), NodeStmt);
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}
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AstNode* wrapIfConstraintMode(AstClass* classp, AstConstraint* const constrp, AstNode* stmtp) {
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const RandomizeMode rmode = {.asInt = constrp->user1()};
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@ -3919,7 +3925,7 @@ class RandomizeVisitor final : public VNVisitor {
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if (commonPrefixp == exprp) break;
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AstVar* const randVarp = getVarFromRef(exprp);
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AstClass* const classp = VN_AS(randVarp->user2p(), Class);
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AstVar* const randModeVarp = getRandModeVar(classp);
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AstVar* const randModeVarp = getRandModeVarFromClass(classp);
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if (savedRandModeVarps.find(randModeVarp) == savedRandModeVarps.end()) {
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AstVar* const randModeTmpVarp
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= makeTmpRandModeVar(exprp, randModeVarp, storeStmtsp, restoreStmtsp);
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@ -4166,7 +4172,7 @@ class RandomizeVisitor final : public VNVisitor {
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FileLine* fl = nodep->fileline();
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AstFunc* const randomizep = V3Randomize::newRandomizeFunc(m_memberMap, nodep);
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AstVar* const fvarp = VN_AS(randomizep->fvarp(), Var);
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AstVar* const randModeVarp = getRandModeVar(nodep);
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AstVar* const randModeVarp = getRandModeVarFromClass(nodep);
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addPrePostCall(nodep, randomizep, "pre_randomize");
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// Call nested pre_randomize on rand class-type members (IEEE 18.4.1)
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@ -4549,7 +4555,7 @@ class RandomizeVisitor final : public VNVisitor {
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UASSERT_OBJ(randModeTarget.classp, nodep,
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"Should have checked in RandomizeMarkVisitor");
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AstVar* const receiverp = randModeTarget.receiverp;
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AstVar* const randModeVarp = getRandModeVar(randModeTarget.classp);
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AstVar* const randModeVarp = getRandModeVarFromClass(randModeTarget.classp);
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AstNodeExpr* const lhsp = makeModeAssignLhs(nodep->fileline(), randModeTarget.classp,
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randModeTarget.fromp, randModeVarp);
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replaceWithModeAssign(nodep,
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@ -4797,7 +4803,7 @@ class RandomizeVisitor final : public VNVisitor {
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}
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// Set rand mode if present (not needed if classGenp exists and was copied)
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AstVar* const randModeVarp = getRandModeVar(classp);
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AstVar* const randModeVarp = getRandModeVarFromClass(classp);
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if (!classGenp && randModeVarp) addSetRandMode(randomizeFuncp, localGenp, randModeVarp);
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// Generate constraint setup code and a hardcoded call to the solver
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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if not test.have_solver:
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test.skip("No constraint solver installed")
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,116 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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typedef logic [31:0] uvm_reg_data_t;
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class uvm_object;
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endclass
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class uvm_reg_field extends uvm_object;
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rand uvm_reg_data_t value;
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int unsigned m_size;
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function uvm_reg_data_t get;
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return value;
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endfunction
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function void set_rand_mode(bit rand_mode);
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value.rand_mode(rand_mode);
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uvm_reg_field_valid.constraint_mode(rand_mode);
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endfunction
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function bit get_rand_mode();
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return bit'(value.rand_mode());
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endfunction
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constraint uvm_reg_field_valid {
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if (64'd64 > {32'd0, m_size}) {
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{32'd0, value} < (64'd1 << m_size);
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}
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}
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function void configure(int unsigned size);
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m_size = size;
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endfunction
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endclass
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class uvm_reg extends uvm_object;
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virtual function void build();
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endfunction
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endclass
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class regA extends uvm_reg;
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rand uvm_reg_field fA1;
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rand uvm_reg_field fA2;
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virtual function void build();
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this.fA1 = new;
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this.fA2 = new;
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this.fA1.configure(16);
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this.fA2.configure(16);
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endfunction
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endclass
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class test extends uvm_object;
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regA rg;
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function new;
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rg = new;
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rg.build();
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endfunction
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task run_test;
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uvm_reg_data_t pre_fA1;
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uvm_reg_data_t pre_fA2;
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int rand_ok;
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// Disable fA1, enable fA2
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rg.fA1.set_rand_mode(0);
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rg.fA2.set_rand_mode(1);
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if (rg.fA1.get_rand_mode() != 0) $stop;
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if (rg.fA2.get_rand_mode() != 1) $stop;
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pre_fA1 = rg.fA1.value;
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rand_ok = rg.randomize();
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if (rand_ok != 0) begin
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// fA1 should be unchanged
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if (rg.fA1.get() !== pre_fA1) begin
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$display("%%Error: fA1 changed: got=%0h exp=%0h", rg.fA1.get(), pre_fA1);
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$stop;
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end
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end
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// Re-enable fA1, disable fA2
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rg.fA1.set_rand_mode(1);
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rg.fA2.set_rand_mode(0);
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pre_fA2 = rg.fA2.value;
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rand_ok = rg.randomize();
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if (rand_ok != 0) begin
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// fA2 should be unchanged
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if (rg.fA2.get() !== pre_fA2) begin
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$display("%%Error: fA2 changed: got=%0h exp=%0h", rg.fA2.get(), pre_fA2);
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$stop;
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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endtask
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endclass
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module top;
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initial begin
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test t;
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t = new;
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t.run_test();
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end
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endmodule
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