Merge from master for release.

.codecov.yml

@@ -1,7 +1,7 @@
 ---
 # DESCRIPTION: codecov.io config
 #
-# Copyright 2020-2025 by Wilson Snyder. This program is free software; you
+# Copyright 2020-2026 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.

.github/workflows/build-test.yml

@@ -138,11 +138,11 @@ jobs:
       CCACHE_DIR: ${{ github.workspace }}/.ccache
       CCACHE_LIMIT_MULTIPLE: 0.95
     steps:
-      - uses: actions/checkout@v5
+      - uses: actions/checkout@v6
         with:
           path: repo
       - name: Cache $CCACHE_DIR
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         with:
           path: ${{ env.CCACHE_DIR }}
           key: msbuild-msvc-cmake
@@ -155,7 +155,7 @@ jobs:
       - name: Zip up repository
         run: Compress-Archive -LiteralPath install -DestinationPath verilator.zip
       - name: Upload zip archive
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v6
         with:
           path: ${{ github.workspace }}/repo/verilator.zip
           name: verilator-win.zip

.github/workflows/contributor.yml

@@ -16,5 +16,5 @@ jobs:
     name: "'docs/CONTRIBUTORS' was signed"
     runs-on: ubuntu-24.04
     steps:
-      - uses: actions/checkout@v5
+      - uses: actions/checkout@v6
       - run: test_regress/t/t_dist_contributors.py

.github/workflows/coverage.yml

@@ -74,10 +74,10 @@ jobs:
     runs-on: ubuntu-24.04
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
 
       - name: Download code coverage data
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v7
         with:
           pattern: code-coverage-*
           path: obj_coverage
@@ -113,7 +113,7 @@ jobs:
           sudo apt install lcov
 
       - name: Download repository archive
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v7
         with:
           name: ${{ needs.build.outputs.archive }}
           path: ${{ github.workspace }}
@@ -124,7 +124,7 @@ jobs:
           ls -lsha
 
       - name: Download code coverage data
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v7
         with:
           pattern: code-coverage-*
           path: repo/obj_coverage
@@ -169,14 +169,14 @@ jobs:
           fi
 
       - name: Upload report
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v6
         with:
           path: repo/obj_coverage
           name: coverage-report
 
       - name: Upload notification
         if: ${{ github.event_name == 'pull_request' }}
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v6
         with:
           path: repo/notification
           name: coverage-pr-notification
@@ -192,7 +192,7 @@ jobs:
       # Creating issues requires elevated privilege
       - name: Generate access token
         id: generate-token
-        uses: actions/create-github-app-token@v2.1.4
+        uses: actions/create-github-app-token@v2.2.1
         with:
           app-id: ${{ vars.VERILATOR_CI_ID }}
           private-key: ${{ secrets.VERILATOR_CI_KEY }}

.github/workflows/docker.yml

@@ -39,7 +39,7 @@ jobs:
 
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
 
       - name: Extract context variables
         run: |

.github/workflows/format.yml

@@ -21,23 +21,23 @@ jobs:
       CI_COMMIT: ${{ github.sha }}
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           token: ${{ secrets.GITHUB_TOKEN }}
       - name: Install packages for build
         env:
           CI_BUILD_STAGE_NAME: build
         run: |
-          bash ci/ci-install.bash &&
+          sudo apt install clang-format-18
-          sudo apt-get install clang-format-18 yapf3 &&
+          git config --global user.email "action@example.com"
-          sudo pip3 install gersemi mbake &&
-          git config --global user.email "action@example.com" &&
           git config --global user.name "github action"
       - name: Format code
         run: |
-          autoconf &&
+          autoconf
-          ./configure &&
+          ./configure
-          make -j 2 format CLANGFORMAT=clang-format-18 &&
+          make venv
+          source .venv/bin/activate
+          make -j 2 format CLANGFORMAT=clang-format-18
           git status
       - name: Push
         run: |-

.github/workflows/pages.yml

@@ -6,11 +6,8 @@ name: Pages
 
 on:
   push:
-    branches:
+    branches: [master]
-      - master
+    paths: ["ci/**", ".github/workflows"]
-    paths:
-      - "ci/**"
-      - ".github/workflows"
   workflow_dispatch:
   workflow_run:
     workflows: ["Code coverage"]
@@ -41,7 +38,7 @@ jobs:
       coverage-pr-run-ids: ${{ steps.build.outputs.coverage-pr-run-ids }}
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
       - name: Build pages
         id: build
         env:
@@ -73,11 +70,11 @@ jobs:
     if: ${{ github.repository == 'verilator/verilator' }}
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
       # Use the Verilator CI app to post the comment
       - name: Generate access token
         id: generate-token
-        uses: actions/create-github-app-token@v2.1.4
+        uses: actions/create-github-app-token@v2.2.1
         with:
           app-id: ${{ vars.VERILATOR_CI_ID }}
           private-key: ${{ secrets.VERILATOR_CI_KEY }}

.github/workflows/reusable-build.yml

@@ -61,14 +61,14 @@ jobs:
       CCACHE_MAXSIZE: 1000M  # Per build matrix entry (* 5 = 5000M in total)
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           path: repo
           ref: ${{ inputs.sha }}
           fetch-depth: ${{ inputs.dev-gcov && '0' || '1' }}  # Coverage flow needs full history
 
       - name: Cache $CCACHE_DIR
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         env:
           CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
         with:
@@ -93,7 +93,7 @@ jobs:
           echo "archive=$ARCHIVE" >> "$GITHUB_OUTPUT"
 
       - name: Upload repository archive
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v6
         with:
           path: ${{ github.workspace }}/${{ steps.create-archive.outputs.archive }}
           name: ${{ steps.create-archive.outputs.archive }}

.github/workflows/reusable-lint-py.yml

@@ -27,20 +27,24 @@ jobs:
     name: Sub-lint | Python
     steps:
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           path: repo
 
       - name: Install packages for build
         run: ./ci/ci-install.bash
 
-    # We use specific version numbers, otherwise a Python package
-    # update may add a warning and break our build
-      - name: Install packages for lint
-        run: sudo pip3 install mypy==1.18.2 pylint==3.0.2 ruff==0.1.3 clang sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe ruff
-
       - name: Configure
-        run: autoconf && ./configure --enable-longtests --enable-ccwarn
+        run: |
+          autoconf
+          ./configure --enable-longtests --enable-ccwarn
+
+      - name: Install python dependencies
+        run: |
+          sudo apt install python3-clang
+          make venv
 
       - name: Lint
-        run: make -k lint-py
+        run: |-
+          source .venv/bin/activate
+          make -k lint-py

.github/workflows/reusable-rtlmeter-build.yml

@@ -38,14 +38,14 @@ jobs:
           sudo apt install ccache mold help2man libfl-dev libgoogle-perftools-dev libsystemc-dev
 
       - name: Use saved ccache
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         with:
           path: ccache
           key: rtlmeter-build-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ github.run_id }}-${{ github.run_attempt }}
           restore-keys: rtlmeter-build-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}
 
       - name: Checkout
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           path: repo
           fetch-depth: 0 # Required for 'git describe' used for 'verilator --version'
@@ -68,7 +68,7 @@ jobs:
         run: tar --posix -c -z -f verilator-rtlmeter.tar.gz install
 
       - name: Upload Verilator installation archive
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v6
         with:
           path: verilator-rtlmeter.tar.gz
           name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }}

.github/workflows/reusable-rtlmeter-run.yml

@@ -62,7 +62,7 @@ jobs:
           sudo apt install ccache mold libfl-dev libgoogle-perftools-dev libsystemc-dev
 
       - name: Download Verilator installation archive
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v7
         with:
           name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }}
 
@@ -73,14 +73,14 @@ jobs:
 
       - name: Use saved ccache
         if: ${{ env.CCACHE_DISABLE == 0 }}
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         with:
           path: ${{ env.CCACHE_DIR }}
           key: rtlmeter-run-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ inputs.cases }}-${{ inputs.compileArgs }}-${{ github.run_id }}-${{ github.run_attempt }}
           restore-keys: rtlmeter-run-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ inputs.cases }}-${{ inputs.compileArgs }}
 
       - name: Checkout RTLMeter
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           repository: "verilator/rtlmeter"
           path: rtlmeter
@@ -115,7 +115,7 @@ jobs:
           ./rtlmeter report --steps '*' --metrics '*' ../results-${{ steps.results.outputs.hash }}.json
 
       - name: Upload results
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v6
         with:
           path: results-${{ steps.results.outputs.hash }}.json
           name: rtlmeter-${{ inputs.tag }}-results-${{ steps.results.outputs.hash }}
@@ -124,5 +124,5 @@ jobs:
 
       - name: Report status
         working-directory: rtlmeter
-        run: | # This will fail the job if any of the runs failed
+        run: |-  # This will fail the job if any of the runs failed
           ./rtlmeter run --verbose --cases='${{inputs.cases}}' --compileArgs='${{inputs.compileArgs}}' --executeArgs='${{inputs.executeArgs}}'

.github/workflows/reusable-test.yml

@@ -55,7 +55,7 @@ jobs:
     steps:
 
       - name: Download repository archive
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v7
         with:
           name: ${{ inputs.archive }}
           path: ${{ github.workspace }}
@@ -67,7 +67,7 @@ jobs:
           ls -lsha
 
       - name: Cache $CCACHE_DIR
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         env:
           CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache2
         with:
@@ -77,14 +77,18 @@ jobs:
             ${{ env.CACHE_KEY }}-
 
       - name: Install test dependencies
-        run: ./ci/ci-install.bash
+        run: |
+          ./ci/ci-install.bash
+          make venv
 
       - name: Test
         id: run-test
         continue-on-error: true
         env:
           TESTS: ${{ inputs.suite }}
-        run: ./ci/ci-script.bash
+        run: |
+          source .venv/bin/activate
+          ./ci/ci-script.bash
 
       - name: Combine code coverage data
         if: ${{ inputs.dev-gcov }}
@@ -95,7 +99,7 @@ jobs:
 
       - name: Upload code coverage data
         if: ${{ inputs.dev-gcov }}
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v6
         with:
           path: ${{ github.workspace }}/repo/obj_coverage/verilator-${{ inputs.suite }}.info
           name: code-coverage-${{ inputs.suite }}

.github/workflows/rtlmeter-pr-results.yml

@@ -20,13 +20,13 @@ jobs:
       pull-requests: write
     steps:
       - name: Download report
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v7
         with:
           name: rtlmeter-pr-results
           run-id: ${{ github.event.workflow_run.id }}
           github-token: ${{ secrets.GITHUB_TOKEN }}
       - name: Download PR number
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v7
         with:
           name: pr-number
           run-id: ${{ github.event.workflow_run.id }}
@@ -34,7 +34,7 @@ jobs:
       # Use the Verilator CI app to post the comment
       - name: Generate access token
         id: generate-token
-        uses: actions/create-github-app-token@v2.1.4
+        uses: actions/create-github-app-token@v2.2.1
         with:
           app-id: ${{ vars.VERILATOR_CI_ID }}
           private-key: ${{ secrets.VERILATOR_CI_KEY }}

.github/workflows/rtlmeter.yml

@@ -77,6 +77,7 @@ jobs:
           - "BlackParrot:1x1:*"
           - "BlackParrot:2x2:*"
           - "BlackParrot:4x4:*"
+          - "Caliptra:default:*"
           - "NVDLA:*"
           - "OpenPiton:1x1:*"
           - "OpenPiton:2x2:*"
@@ -122,6 +123,7 @@ jobs:
           - "BlackParrot:1x1:*"
           - "BlackParrot:2x2:*"
           - "BlackParrot:4x4:*"
+          - "Caliptra:default:*"
           - "NVDLA:*"
           - "OpenPiton:1x1:*"
           - "OpenPiton:2x2:*"
@@ -188,7 +190,7 @@ jobs:
         tag: [gcc, clang, gcc-hier]
     steps:
       - name: Checkout RTLMeter
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           repository: "verilator/rtlmeter"
           path: rtlmeter
@@ -196,7 +198,7 @@ jobs:
         working-directory: rtlmeter
         run: make venv
       - name: Download all results
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v7
         with:
           pattern: rtlmeter-${{ matrix.tag }}-results-*
           path: all-results-${{ matrix.tag }}
@@ -206,7 +208,7 @@ jobs:
         run: |
           ./rtlmeter collate ../all-results-${{ matrix.tag }}/*.json > ../all-results-${{ matrix.tag }}.json
       - name: Upload combined results
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v6
         with:
           path: all-results-${{ matrix.tag }}.json
           name: all-results-${{ matrix.tag }}
@@ -225,20 +227,20 @@ jobs:
     runs-on: ubuntu-24.04
     steps:
       - name: Download combined results
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v7
         with:
           pattern: all-results-*
           path: results
           merge-multiple: true
       - name: Upload published results
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v6
         with:
           path: results/*.json
           name: published-results
       # Pushing to verilator/verilator-rtlmeter-results requires elevated permissions
       - name: Generate access token
         id: generate-token
-        uses: actions/create-github-app-token@v2.1.4
+        uses: actions/create-github-app-token@v2.2.1
         with:
           app-id: ${{ vars.VERILATOR_CI_ID }}
           private-key: ${{ secrets.VERILATOR_CI_KEY }}
@@ -246,7 +248,7 @@ jobs:
           repositories: verilator-rtlmeter-results
           permission-contents: write
       - name: Checkout verilator-rtlmeter-results
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           repository: "verilator/verilator-rtlmeter-results"
           token: ${{ steps.generate-token.outputs.token }}
@@ -279,7 +281,7 @@ jobs:
       actions: read
     steps:
       - name: Checkout RTLMeter
-        uses: actions/checkout@v5
+        uses: actions/checkout@v6
         with:
           repository: "verilator/rtlmeter"
           path: rtlmeter
@@ -287,7 +289,7 @@ jobs:
         working-directory: rtlmeter
         run: make venv
       - name: Download combined results
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v7
         with:
           pattern: all-results-*
           path: all-results
@@ -306,7 +308,7 @@ jobs:
           DATE=$(gh run --repo ${{ github.repository }} view $ID --json createdAt --jq ".createdAt")
           echo "date=$DATE" >> $GITHUB_OUTPUT
       - name: Download scheduled run results
-        uses: actions/download-artifact@v6
+        uses: actions/download-artifact@v7
         with:
           name: published-results
           path: nightly-results
@@ -372,14 +374,14 @@ jobs:
           done
           cat report.txt
       - name: Upload report
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v6
         with:
           path: report.txt
           name: rtlmeter-pr-results
       - name: Save PR number
         run: echo ${{ github.event.number }} > pr-number.txt
       - name: Upload PR number
-        uses: actions/upload-artifact@v5
+        uses: actions/upload-artifact@v6
         with:
           path: pr-number.txt
           name: pr-number
@@ -395,7 +397,7 @@ jobs:
       # Creating issues requires elevated privilege
       - name: Generate access token
         id: generate-token
-        uses: actions/create-github-app-token@v2.1.4
+        uses: actions/create-github-app-token@v2.2.1
         with:
           app-id: ${{ vars.VERILATOR_CI_ID }}
           private-key: ${{ secrets.VERILATOR_CI_KEY }}

.gitignore

@@ -17,6 +17,7 @@
 *.pdf
 /Makefile
 /.ccache
+/.venv/
 /artifact/
 README
 TAGS

CITATION.cff

@@ -1,3 +1,4 @@
+---
 # See https://citation-file-format.github.io/
 cff-version: 1.2.0
 title: Verilator
@@ -14,14 +15,14 @@ authors:
     family-names: Wasson
   - given-names: Duane
     family-names: Galbi
+  - given-names: Geza
+    family-names: Lore
   - name: 'et al'
 repository-code: 'https://github.com/verilator/verilator'
 url: 'https://verilator.org'
 abstract: >-
   The Verilator package converts Verilog and SystemVerilog hardware
   description language (HDL) designs into a fast C++ or SystemC model
-  that, after compiling, can be executed.  Verilator is not a
+  that, after compiling, can be executed.  Verilator is not only a
   traditional simulator but a compiler.
-license:
+license: [LGPL-3.0-only, Artistic-2.0]
-  - LGPL-3.0-only
-  - Artistic-2.0

CMakeLists.txt

@@ -4,7 +4,7 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2026 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -16,7 +16,7 @@ cmake_minimum_required(VERSION 3.15)
 cmake_policy(SET CMP0091 NEW) # Use MSVC_RUNTIME_LIBRARY to select the runtime
 project(
     Verilator
-    VERSION 5.042
+    VERSION 5.044
     HOMEPAGE_URL https://verilator.org
     LANGUAGES CXX
 )

Changes

@@ -8,6 +8,130 @@ The changes in each Verilator version are described below.  The
 contributors that suggested or implemented a given issue are shown in []. Thanks!
 
 
+Verilator 5.044 2026-01-01
+==========================
+
+**Important:**
+
+* This is the last release supporting the deprecated `--xml-only` and
+  `--make cmake` options.
+* Change `--lint-only` and `--json-only` to imply `--timing` (#6790).
+
+**Other:**
+
+* Add `--unroll-limit` option (#6654) (#6668). [Geza Lore, Fractile Ltd.]
+* Add `-fno-inline-funcs-eager` option to disable excessive inlining (#6682). [Geza Lore, Fractile Ltd.]
+* Add `-param`/`-port` options to `public_flat*` control directives (#6685). [Geza Lore, Fractile Ltd.]
+* Add `--top` specifying `config` name (#6710). [Dan Ruelas-Petrisko]
+* Add `sc_biguint` pragma (#6712). [Jakub Wasilewski, Antmicro Ltd.]
+* Add `make venv` target (#6775). [Geza Lore]
+* Add SUPERNFIRST error on super.new on non-first statement (#6784). [Artur Bieniek]
+* Add fargs for reusability of `--dump-inputs` output (#6812). [Geza Lore]
+* Add `--quiet-build` to suppress make/compiler informationals.
+* Support `std::randomize(){...}` (#4706) (#6573). [Yilou Wang]
+* Support force assignments to unpacked array elements (partial #4735) (#6787). [Ryszard Rozak, Antmicro Ltd.]
+* Support `config' (#5891) (#6714) (#6717) (#6745) (#6764). [Dan Ruelas-Petrisko]
+* Support unpacked struct in localparam (#6053 partial) (#6708). [Jonathan Drolet]
+* Support `randsequence` (#6131).
+* Support array reference arguments into 'std::randomize()' (#6384) (#6719). [Yilou Wang]
+* Support basic global constraints (#6551) (#6552). [Yilou Wang]
+* Support SystemC time resolution with step 10/100 (#6633) (#6715). [Aliaksei Chapyzhenka]
+* Support `this.randomize()` with constraints (#6634). [Artur Bieniek, Antmicro Ltd.]
+* Support multi-expression sequences (#6639). [Bartłomiej Chmiel, Antmicro Ltd.]
+* Support `#1step` delay as statement  (#6671). [Pawel Kojma, Antmicro Ltd.]
+* Support clocking output delay `1step` (#6681). [Ondrej Ille]
+* Support parsing of dotted `bins_expression` (#6683). [Pawel Kojma, Antmicro Ltd.]
+* Support constant expression cycle delays in sequences (#6691). [Ryszard Rozak, Antmicro Ltd.]
+* Support general global constraints (#6709) (#6711). [Yilou Wang]
+* Support complex std::randomize patterns (#6736) (#6737). [Yilou Wang]
+* Support `rand_mode` in global constraint gathering (#6740) (#6752). [Yilou Wang]
+* Support reduction or in constraints (#6840). [Pawel Kojma, Antmicro Ltd.]
+* Support vpiSigned (#6868) (#6870). [Kaleb Barrett]
+* Optimize away calls to empty functions (#6626). [Geza Lore]
+* Optimize redundant headers in Syms implementation files. [Geza Lore, Fractile Ltd.]
+* Optimize constructor/destructor VerilatedModules (#6660). [Geza Lore, Fractile Ltd.]
+* Optimize repeated function call during symbol table initialization (#6665). [Geza Lore, Fractile Ltd.]
+* Optimize functions reading external parameters as pure (#6684). [Geza Lore, Fractile Ltd.]
+* Optimize `$past` delayed variable reuse (#6689). [Geza Lore, Fractile Ltd.]
+* Optimize combinational loops through sign extension (#6724). [Geza Lore]
+* Optimize trace initialization code size (#6749). [Geza Lore]
+* Optimize combinational cycles in DFG (#6744) (#6746) (#6744). [Geza Lore]
+* Optimize inlining small C functions and add `-inline-cfuncs` (#6815). [Jose Drowne]
+* Fix generate function(s) inside of generate blocks (#1011) (#6789). [em2machine]
+* Fix typedef derived from type defined inside interface (#3441) (#6776). [em2machine]
+* Fix warning lint directive ordering and consistency (#4185) (#5368) (#5610) (#6876).
+* Fix extern function that returns parameterized class (#4924).
+* Fix type deduction for variable parameterized classes (#6281) (#6813). [em2machine]
+* Fix randomize called within func/task (#6144) (#6753). [Yilou Wang]
+* Fix pre/post_randomize on extended classes (#6467). [Alex Solomatnikov]
+* Fix expression short circuiting (#6483). [Todd Strader]
+* Fix resized lvalues with warning suppressed (#6497) (#6816). [Alex Solomatnikov]
+* Fix unsupported `if` virtual interface warning (#6558) (#6861). [Krzysztof Bieganski, Antmicro Ltd.]
+* Fix expression coverage of system calls (#6592). [Todd Strader]
+* Fix `--timing` with `--x-initial-edge` (#6603) (#6631). [Krzysztof Bieganski, Antmicro Ltd.]
+* Fix merging of impure assignments in gate optimization (#6629) (#6630). [Geza Lore]
+* Fix determining Verilator revision when within git submodules without tags.
+* Fix initial random values for verilator-created variables (#6611). [Todd Strader]
+* Fix parsing of `with` clause inside covergroups (#6618). [Pawel Kojma, Antmicro Ltd.]
+* Fix slice memory overflow on large output arrays (#6636) (#6638). [Jens Yuechao Liu]
+* Fix localparam type assignment from interface type parameters (#6637) (#6732). [em2machine]
+* Fix memory usage statistics on MacOS (#6644). [Geza Lore, Fractile Ltd.]
+* Fix command line statistics with --stats (#6645) (#6646). [Geza Lore, Fractile Ltd.]
+* Fix slow compilation of generated sampled value code (#6652). [Geza Lore, Fractile Ltd.]
+* Fix non-deterministic output when splitting Syms file. [Geza Lore, Fractile Ltd.]
+* Fix crash on DFG driver lookup (#6649). [Geza Lore]
+* Fix ccache-report with PCH files. [Geza Lore, Fractile Ltd.]
+* Fix parameterized class function (#6659) (#6802). [em2machine]
+* Fix local interface parameter hierarchical access (#6661) (#6666). [Paul Swirhun]
+* Fix splitting of Syms constructor/destructor bodies (#6662). [Geza Lore, Fractile Ltd.]
+* Fix long C++ compilation due to VerilatedScope constructors (#6664). [Geza Lore, Fractile Ltd.]
+* Fix large array initialization (#6669). [Artur Bieniek, Antmicro Ltd.]
+* Fix `--expand-limit` not respected for expressions (#6670). [Geza Lore, Fractile Ltd.]
+* Fix `free` name collision (#6675). [Todd Strader]
+* Fix bounds checking in non-inlined function (#6677). [Geza Lore, Fractile Ltd.]
+* Fix stream operator widening (#6693) (#6697). [Jean-Nicolas Strauss]
+* Fix multitop cross references (#6699).
+* Fix DFG independent bits analysis performance (#6713) (#6743). [Geza Lore]
+* Fix deleting linked node error in V3Randomize (#6718). [Igor Zaworski, Antmicro Ltd.]
+* Fix runtime worker thread stack sizes on MacOS (#6721). [Geza Lore]
+* Fix X handling in UDPs (#6722) (#6723). [Michael Bikovitsky]
+* Fix `--prof-exec` using `--lib-create`. [Geza Lore]
+* Fix fork scheduling semantics (#6730). [Artur Bieniek, Antmicro Ltd.]
+* Fix JSON output case statements (#6733).
+* Fix internal fault when cross-class calling with DPI (#6735) (#6742). [Matthew Ballance]
+* Fix write variable placement for global constraints (#6740) (#6750) (#6797). [Yilou Wang]
+* Fix JSON dump missing output ports (#6751) (#6831). [Oleh Maksymenko]
+* Fix resolution of specialized typedefs (#6754) (#6808) (#6834). [em2machine]
+* Fix UNSUPPORTED on force / release with complex selects (#6755). [Ryszard Rozak, Antmicro Ltd.]
+* Fix select assignment expansion (#6757). [Geza Lore]
+* Fix `--lib-create` with multi-bit clocks (#6759). [Geza Lore]
+* Fix DFG reusing volatile variables. [Geza Lore]
+* Fix DFG assertion on out-of-bounds selects. [Geza Lore]
+* Fix process reference giving no return statement error (#6767) (#6823). [Krzysztof Bieganski, Antmicro Ltd.]
+* Fix class param static not found again error (#6768).
+* Fix crash when super.new() called without a base class (#6772). [Matthew Ballance]
+* Fix class-in-class extends with parameters (#6773).
+* Fix enum item references in class extends with parameters.
+* Fix reordering of function body inlined on RHS of <= NBA (#6780). [Geza Lore]
+* Fix clang `-Wno-vla-cxx-extension` warning for UVM DPI tests (#6782)
+* Fix `disable iff` in simple properties (#6783). [Ryszard Rozak, Antmicro Ltd.]
+* Fix input sampling of clocking block signals (#6788). [Pawel Kojma, Antmicro Ltd.]
+* Fix O(n*2) analysis in const-bit-op-tree (#6791). [Geza Lore]
+* Fix member select of variable without randmode (#6800) (#6833). [Yilou Wang]
+* Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle]
+* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
+* Fix setting thread count in VerilatedContext (#6826 partial) (#6841). [Yangyu Chen]
+* Fix firing array selects of events (#6829). [Amal Araweelo Almis]
+* Fix false IMPLICITSTATIC on localparam (#6835). [Geza Lore]
+* Fix randcase under fork (#6843). [Amal Araweelo Almis]
+* Fix JSON missing `signed` indication (#6845).
+* Fix class reference throwing cannot detect changes error (#6851).
+* Fix `randc` on extended class (#6852).
+* Fix typedef `::` class reference error (#6862).
+* Fix missing include on FreeBSD (#6864).
+* Fix `--Wwarn-lint` to be inverse of `--Wno-lint`.
+
+
 Verilator 5.042 2025-11-02
 ==========================
 
@@ -39,6 +163,7 @@ Verilator 5.042 2025-11-02
 * Support modports referencing clocking blocks (#4555) (#6436). [Ryszard Rozak, Antmicro Ltd.]
 * Support class package reference on pattern keys (#5653). [Todd Strader]
 * Support digits in `$sscanf` field width formats (#6083). [Iztok Jeras]
+* Support assert under assert (#6146). [Alex Solomatnikov]
 * Support pure functions in sensitivity lists (#6393). [Krzysztof Bieganski, Antmicro Ltd.]
 * Support simple alias statements (#6339) (#6501). [Ryszard Rozak, Antmicro Ltd.]
 * Support simple cycle delay sequence expressions inside properties (#6508). [Bartłomiej Chmiel, Antmicro Ltd.]
@@ -445,6 +570,7 @@ Verilator 5.034 2025-02-24
 * Optimize labels as final `if` block statements (#5744).
 * Optimize empty function definition bodies (#5750).
 * Optimize splitting trigger computation and dump (#5798). [Geza Lore]
+* Optimize some DFG multiplexers (#6822). [Yangyu Chen]
 * Fix error message when call task as a function (#3089). [Matthew Ballance]
 * Fix force VPI public signal visibility (#5225). [Frédéric Requin]
 * Fix VPI iteration over hierarchy (#5314) (#5731). [Natan Kreimer]
@@ -5394,7 +5520,7 @@ Verilator 0.0 1994-07-08
 Copyright
 =========
 
-Copyright 2001-2025 by Wilson Snyder. This program is free software; you
+Copyright 2001-2026 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

Makefile.in

@@ -7,7 +7,7 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2026 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -460,23 +460,19 @@ analyzer-include:
 	-rm -rf examples/*/obj*
 	scan-build $(MAKE) -k examples
 
-format:
+# Bash/sh files
-	$(MAKE) -j 5 format-c format-cmake format-exec format-py
+BASH_FILES = \
-
+  ci/ci-install.bash \
-CLANGFORMAT = clang-format-18
+  ci/ci-pages-notify.bash \
-CLANGFORMAT_FLAGS = -i
+  ci/ci-pages.bash \
-CLANGFORMAT_FILES = $(CHECK_CPP) $(CHECK_H) $(CHECK_YL) test_regress/t/*.c* test_regress/t/*.h
+  ci/ci-script.bash \
-
+  ci/docker/run/hooks/post_push \
-format-c clang-format:
+  ci/docker/run/verilator-docker \
-	$(CLANGFORMAT) --version
+  ci/docker/run/verilator-wrap.sh \
-	@$(CLANGFORMAT) --version | fgrep 'version 18' > /dev/null \
+  nodist/fuzzer/all \
-	|| echo "*** You are not using clang-format-18, indents may differ from master's ***"
+  nodist/fuzzer/run \
-	$(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES)
+  nodist/fuzzer/setup_root \
-
+  nodist/fuzzer/setup_user \
-YAMLFIX = YAMLFIX_WHITELINES=1 YAMLFIX_LINE_LENGTH=200 YAMLFIX_preserve_quotes=true yamlfix
-
-yamlfix:
-	$(YAMLFIX) .
 
 # CMake files
 CMAKE_FILES = \
@@ -495,6 +491,12 @@ MAKE_FILES = \
   src/Makefile*.in \
   test_regress/Makefile* \
 
+# Perl programs
+PERL_PROGRAMS = \
+  bin/redirect \
+  bin/verilator \
+  bin/verilator_coverage \
+
 # Python programs, subject to format and lint
 PY_PROGRAMS = \
   bin/verilator_ccache_report \
@@ -502,25 +504,28 @@ PY_PROGRAMS = \
   bin/verilator_gantt \
   bin/verilator_includer \
   bin/verilator_profcfunc \
-  examples/json_py/vl_file_copy \
-  examples/json_py/vl_hier_graph \
-  docs/guide/conf.py \
   docs/bin/vl_sphinx_extract \
   docs/bin/vl_sphinx_fix \
-  src/astgen \
+  docs/guide/conf.py \
-  src/bisonpre \
+  examples/json_py/vl_file_copy \
-  src/config_rev \
+  examples/json_py/vl_hier_graph \
-  src/flexfix \
-  src/vlcovgen \
-  src/.gdbinit.py \
-  test_regress/*.py \
-  test_regress/t/*.pf \
   nodist/clang_check_attributes \
   nodist/dot_importer \
   nodist/fuzzer/actual_fail \
   nodist/fuzzer/generate_dictionary \
   nodist/install_test \
+  nodist/lint_py_test_filter \
   nodist/log_changes \
+  nodist/uvm_pkg_packer \
+  nodist/verilator_saif_diff \
+  src/.gdbinit.py \
+  src/astgen \
+  src/bisonpre \
+  src/config_rev \
+  src/flexfix \
+  src/vlcovgen \
+  test_regress/*.py \
+  test_regress/t/*.pf \
 
 # Python files, subject to format but not lint
 PY_FILES = \
@@ -530,26 +535,70 @@ PY_FILES = \
 # Python files, test_regress tests
 PY_TEST_FILES = test_regress/t/*.py
 
-YAPF = yapf3
+# YAML files
+YAML_FILES = \
+  .*.yaml \
+  .*.yml \
+  .github/*.yml \
+  .github/*/*.yml \
+  CITATION.cff \
+
+######################################################################
+# Format
+
+format:
+	$(MAKE) -j 5 format-c format-cmake format-exec format-py format-yaml
+
+BEAUTYSH = beautysh
+BEAUTYSH_FLAGS = --indent-size 2
+
+format-bash:
+	$(BEAUTYSH) --version
+	$(BEAUTYSH) $(BEAUTYSH_FLAGS) $(BASH_FILES)
+
+CLANGFORMAT = clang-format-18
+CLANGFORMAT_FLAGS = -i
+CLANGFORMAT_FILES = $(CHECK_CPP) $(CHECK_H) $(CHECK_YL) test_regress/t/*.c* test_regress/t/*.h
+
+format-c clang-format:
+	$(CLANGFORMAT) --version
+	@$(CLANGFORMAT) --version | fgrep 'version 18' > /dev/null \
+	|| echo "*** You are not using clang-format-18, indents may differ from master's ***"
+	$(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES)
+
+GERSEMI = gersemi
+GERSEMI_FLAGS = -i --no-warn-about-unknown-commands
+
+format-cmake:
+	$(GERSEMI) --version
+	$(GERSEMI) $(GERSEMI_FLAGS) $(CMAKE_FILES)
+
+MBAKE = mbake
+MBAKE_FLAGS = format --config ./.bake.toml
+
+format-exec:
+	-chmod a+x test_regress/t/*.py
+
+format-make mbake:
+	$(MBAKE) --version
+	$(MBAKE) $(MBAKE_FLAGS) $(MAKE_FILES)
+
+YAPF = yapf
 YAPF_FLAGS = -i --parallel
 
 format-py yapf:
 	$(YAPF) --version
 	$(YAPF) $(YAPF_FLAGS) $(PY_FILES)
 
-GERSEMI = gersemi
+YAMLFIX = YAMLFIX_WHITELINES=1 YAMLFIX_LINE_LENGTH=200 YAMLFIX_preserve_quotes=true yamlfix
-GERSEMI_FLAGS = -i --no-warn-about-unknown-commands
+YAMLFIX_FLAGS =
 
-format-cmake:
+format-yaml yamlfix:
-	$(GERSEMI) $(GERSEMI_FLAGS) $(CMAKE_FILES)
+	$(YAMLFIX) --version
+	$(YAMLFIX) $(YAMLFIX_FLAGS) $(YAML_FILES)
 
-MBAKE = mbake
+######################################################################
-MBAKE_FLAGS = format --config ./.bake.toml
+# Lint
-
-format-make:
-	$(MBAKE) $(MBAKE_FLAGS) $(MAKE_FILES)
-
-format-yaml: yamlfix
 
 MYPY = mypy
 MYPY_FLAGS = --strict --no-error-summary
@@ -583,9 +632,6 @@ lint-py-pylint-tests:
 lint-py-ruff:
 	$(RUFF) $(RUFF_FLAGS) $(PY_PROGRAMS)
 
-format-exec:
-	-chmod a+x test_regress/t/*.py
-
 ######################################################################
 # Configure
 
@@ -781,7 +827,7 @@ clean mostlyclean distclean maintainer-clean::
 
 distclean maintainer-clean::
 	rm -f *.info* *.1 $(INFOS) $(INFOS_OLD) $(VL_INST_MAN_FILES)
-	rm -f Makefile config.status config.cache config.log TAGS
+	rm -f Makefile config.status config.cache config.log configure~ TAGS
 	rm -f verilator_bin* verilator_coverage_bin*
 	rm -f bin/verilator_bin* bin/verilator_coverage_bin*
 	rm -f include/verilated.mk include/verilated_config.h
@@ -806,3 +852,20 @@ preexist:
 
 maintainer-dist: preexist tag
 	svnorcvs release $(DISTTAGNAME)
+
+######################################################################
+# Python venv
+
+VENV_PATH ?= .venv
+
+.PHONY: venv
+venv:
+	# Create virtual environment using the python3 picked up by configure
+	[ -e $(VENV_PATH) ] || @PYTHON3@ -m venv --system-site-packages $(VENV_PATH)
+	# Install python3 dependencies
+	$(VENV_PATH)/bin/pip3 install -r python-dev-requirements.txt
+	@echo
+	@echo "Installed Python virtual environment, in:"
+	@echo "  $(VENV_PATH)"
+	@echo "To activate, run:"
+	@echo "  source $(VENV_PATH)/bin/activate"

README.rst

@@ -69,21 +69,21 @@ Verilated generated libraries, optionally encrypted, into other simulators.
 Verilator may not be the best choice if you are expecting a full-featured
 replacement for a closed-source Verilog simulator, need SDF annotation,
 mixed-signal simulation, or are doing a quick class project (we recommend
-`Icarus Verilog`_ for classwork).  However, if you are looking for a path
+`Icarus Verilog`_ for classwork). However, if you are looking for a path to
-to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
+migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
 designs, Verilator is the tool for you.
 
 
 Performance
 ===========
 
-Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather,
+Verilator does not directly translate Verilog HDL to C++ or SystemC.
-Verilator compiles your code into a much faster optimized and optionally
+Rather, Verilator compiles your code into a much faster optimized and
-thread-partitioned model, which is in turn wrapped inside a C++/SystemC
+optionally thread-partitioned model, which is in turn wrapped inside a
-module. The results are a compiled Verilog model that executes even on a
+C++/SystemC module. The results are a compiled Verilog model that executes
-single thread over 10x faster than standalone SystemC, and on a single
+even on a single thread over 10x faster than standalone SystemC, and on a
-thread is about 100 times faster than interpreted Verilog simulators such
+single thread is about 100 times faster than interpreted Verilog simulators
-as `Icarus Verilog`_. Another 2-10x speedup might be gained from
+such as `Icarus Verilog`_. Another 2-10x speedup might be gained from
 multithreading (yielding 200-1000x total over interpreted simulators).
 
 Verilator has typically similar or better performance versus closed-source
@@ -101,8 +101,8 @@ For more information:
 - `Verilator installation and package directory structure
   <https://verilator.org/install>`_
 
-- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_,
+- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or
-  or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
+  `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
 
 - `Subscribe to Verilator announcements
   <https://github.com/verilator/verilator-announce>`_
@@ -145,16 +145,16 @@ Related Projects
 Open License
 ============
 
-Verilator is Copyright 2003-2025 by Wilson Snyder. (Report bugs to
+Verilator is Copyright 2003-2026 by Wilson Snyder. (Report bugs to
 `Verilator Issues <https://verilator.org/issues>`_.)
 
 Verilator is free software; you can redistribute it and/or modify it under
 the terms of either the GNU Lesser General Public License Version 3 or the
 Perl Artistic License Version 2.0. See the documentation for more details.
 
-.. _CHIPS Alliance: https://chipsalliance.org
+.. _chips alliance: https://chipsalliance.org
-.. _Icarus Verilog: https://steveicarus.github.io/iverilog
+.. _icarus verilog: https://steveicarus.github.io/iverilog
-.. _Linux Foundation: https://www.linuxfoundation.org
+.. _linux foundation: https://www.linuxfoundation.org
 .. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png
 .. |verilator multithreaded performance| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png
 .. |verilator usage| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png

bin/redirect

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2026 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.

bin/verilator

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2026 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -42,6 +42,7 @@ if ($#ARGV < 0) {
 }
 
 # Insert debugging options up front
+# (VERILATOR_TEST_FLAGS is not a documented nor official supported feature)
 push @ARGV, (split ' ', $ENV{VERILATOR_TEST_FLAGS} || "");
 
 # We sneak a look at the flags so we can do some pre-environment checks
@@ -408,6 +409,8 @@ detailed descriptions of these arguments.
      -I<dir>                    Directory to search for includes
     --if-depth <value>          Tune IFDEPTH warning
      +incdir+<dir>              Directory to search for includes
+    --inline-cfuncs <value>     Inline CFuncs with <=value nodes (0=off)
+    --inline-cfuncs-product <value>  Inline CFuncs if size*calls <= value
     --inline-mult <value>       Tune module inlining
     --instr-count-dpi <value>   Assumed dynamic instruction count of DPI imports
      -j <jobs>                  Parallelism for --build-jobs/--verilate-jobs
@@ -419,6 +422,7 @@ detailed descriptions of these arguments.
     --l2-name <value>           Verilog scope name of the top module
     --language <lang>           Default language standard to parse
      -LDFLAGS <flags>           Linker pre-object arguments for makefile
+     -libmap                    Specify library mapping file
     --lib-create <name>         Create a DPI library
      +libext+<ext>+[ext]...     Extensions for finding modules
      +librescan                 Ignored for compatibility
@@ -473,6 +477,7 @@ detailed descriptions of these arguments.
     --public-params             Mark all parameters as public_flat
      -pvalue+<name>=<value>     Overwrite toplevel parameter
     --quiet                     Minimize additional printing
+    --quiet-build               Don't print build progress
     --quiet-exit                Don't print the command on failure
     --quiet-stats               Don't print statistics
     --relative-includes         Resolve includes relative to current file
@@ -517,6 +522,7 @@ detailed descriptions of these arguments.
      -U<var>                    Undefine preprocessor define
     --no-unlimited-stack        Don't disable stack size limit
     --unroll-count <loops>      Tune maximum loop iterations
+    --unroll-limit <loops>      Maximum loop iterations before assuming infinite loop
     --unroll-stmts <stmts>      Tune maximum loop body size
     --unused-regexp <regexp>    Tune UNUSED lint signals
      -V                         Verbose version and config
@@ -578,7 +584,7 @@ description of these arguments.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2025 by Wilson Snyder. This program is free software; you can
+Copyright 2003-2026 by Wilson Snyder. This program is free software; you can
 redistribute it and/or modify the Verilator internals under the terms of
 either the GNU Lesser General Public License Version 3 or the Perl Artistic
 License Version 2.0.

bin/verilator_ccache_report

@@ -17,18 +17,14 @@ parser = argparse.ArgumentParser(
 
     For documentation see
     https://verilator.org/guide/latest/exe_verilator_ccache_report.html""",
-    epilog="""Copyright 2002-2025 by Wilson Snyder. This program is free software; you
+    epilog="""Copyright 2002-2026 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
 SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-parser.add_argument('-o',
+parser.add_argument('-o', type=pathlib.Path, metavar="OUTFILE", required=True, help='output file')
-                    type=argparse.FileType('w'),
-                    metavar="OUTFILE",
-                    required=True,
-                    help='output file')
 parser.add_argument('logdir', type=pathlib.Path, help='log directory')
 
 args = parser.parse_args()
@@ -58,34 +54,35 @@ for logfile in args.logdir.iterdir():
                 elapsed[obj] = toDateTime(match.group(1)) - start
                 results[obj] = match.group(2)
 
-args.o.write("#" * 80 + "\n")
+with args.o.open("w") as ofd:
-args.o.write("ccache report (from verilator_ccache_report) :\n")
+    ofd.write("#" * 80 + "\n")
+    ofd.write("ccache report (from verilator_ccache_report) :\n")
 
-if not results:
+    if not results:
-    args.o.write("\nAll object files up to date\n")
+        ofd.write("\nAll object files up to date\n")
-else:
+    else:
-    args.o.write("\nCompiled object files:\n")
+        ofd.write("\nCompiled object files:\n")
         wnames = max(len(_) for _ in results) + 1
         wresults = max(len(_) for _ in results.values()) + 1
         for k in sorted(results.keys()):
-        args.o.write("{:{wnames}} : {:{wresults}} : {}s\n".format(k,
+            ofd.write("{:{wnames}} : {:{wresults}} : {}s\n".format(k,
                                                                    results[k],
                                                                    elapsed[k].total_seconds(),
                                                                    wnames=wnames,
                                                                    wresults=wresults))
 
-    args.o.write("\nSummary:\n")
+        ofd.write("\nSummary:\n")
         counts = collections.Counter(_ for _ in results.values())
         total = sum(counts.values())
         for k in sorted(counts.keys()):
             c = counts[k]
-        args.o.write("{:{width}}| {} ({:.2%})\n".format(k, c, c / total, width=wresults))
+            ofd.write("{:{width}}| {} ({:.2%})\n".format(k, c, c / total, width=wresults))
 
-    args.o.write("\nLongest:\n")
+        ofd.write("\nLongest:\n")
         longest = sorted(list(elapsed.items()), key=lambda kv: -kv[1].total_seconds())
         for i, (k, v) in enumerate(longest):
-        args.o.write("{:{width}}| {}s\n".format(k, v.total_seconds(), width=wnames))
+            ofd.write("{:{width}}| {}s\n".format(k, v.total_seconds(), width=wnames))
             if i > 4:
                 break
 
-args.o.write("#" * 80 + "\n")
+    ofd.write("#" * 80 + "\n")

bin/verilator_coverage

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2026 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -192,7 +192,7 @@ L<https://verilator.org/guide/latest/exe_verilator_coverage.html>.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+Copyright 2003-2026 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.

bin/verilator_difftree

@@ -110,7 +110,7 @@ It performs a diff between two files, or all files common between two
 directories, ignoring irrelevant pointer differences.
 
 Exit status is 0 if inputs are the same, 1 if different, 2 if trouble.""",
-    epilog="""Copyright 2005-2025 by Wilson Snyder. This program is free software; you
+    epilog="""Copyright 2005-2026 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

bin/verilator_gantt

@@ -613,7 +613,7 @@ Verilator_gantt creates a visual representation to help analyze Verilator
 
 For documentation see
 https://verilator.org/guide/latest/exe_verilator_gantt.html""",
-    epilog="""Copyright 2018-2025 by Wilson Snyder. This program is free software; you
+    epilog="""Copyright 2018-2026 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

bin/verilator_includer

@@ -2,7 +2,7 @@
 # mypy: disallow-untyped-defs
 # pylint: disable=C0114,C0209
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2026 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify the Verilator internals under the terms
 # of either the GNU Lesser General Public License Version 3 or the Perl
 # Artistic License Version 2.0.

bin/verilator_profcfunc

@@ -173,7 +173,7 @@ in each Verilog block.
 
 For documentation see
 https://verilator.org/guide/latest/exe_verilator_profcfunc.html""",
-    epilog="""Copyright 2002-2025 by Wilson Snyder. This program is free software; you
+    epilog="""Copyright 2002-2026 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

ci/docker/buildenv/README.rst

@@ -1,7 +1,7 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Verilator Build Docker Container:
+.. _verilator build docker container:
 
 Verilator Build Docker Container
 ================================
@@ -37,8 +37,9 @@ To change the compiler use the `-e` switch to pass environment variables:
 
    docker run -ti -e CXX=clang++-18 verilator/verilator-buildenv test
 
-The tests, that involve numactl are not working due to security restrictions.
+The tests, that involve numactl are not working due to security
-To run those too, add the CAP_SYS_NICE capability during the start of the container:
+restrictions. To run those too, add the CAP_SYS_NICE capability during the
+start of the container:
 
 ::
 

ci/docker/run/README.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Verilator Executable Docker Container
@@ -11,12 +11,12 @@ easily as a docker image, e.g.:
 
    docker run -ti verilator/verilator:latest --version
 
-This will pull the container from `docker hub
+This will pull the container from `Docker Hub
-<https://hub.docker.com/r/verilator/verilator>`_, run the latest Verilator and print
+<https://hub.docker.com/r/verilator/verilator>`_, run the latest Verilator
-Verilator's version.
+and print Verilator's version.
 
-Containers are automatically built and pushed to docker hub for all released versions, so you may
+Containers are automatically built and pushed to docker hub for all
-easily compare results across versions, e.g.:
+released versions, so you may easily compare results across versions, e.g.:
 
 ::
 
@@ -68,9 +68,9 @@ Internals
 The Dockerfile builds Verilator and removes the tree when completed to
 reduce the image size. The entrypoint is a wrapper script
 (``verilator-wrap.sh``). That script 1. calls Verilator, and 2. copies the
-Verilated runtime files to the ``obj_dir`` or the ``-Mdir``
+Verilated runtime files to the ``obj_dir`` or the ``-Mdir`` respectively.
-respectively. This allows the user to have the files to they may later
+This allows the user to have the files to they may later build the C++
-build the C++ output with the matching runtime files. The wrapper also
+output with the matching runtime files. The wrapper also patches the
-patches the Verilated Makefile accordingly.
+Verilated Makefile accordingly.
 
 A hook is also defined and run by Docker Hub via automated builds.

configure.ac

@@ -1,6 +1,6 @@
 # DESCRIPTION: Process this file with autoconf to produce a configure script.
 #
-# Copyright 2003-2025 by Wilson Snyder. Verilator is free software; you
+# Copyright 2003-2026 by Wilson Snyder. Verilator is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU Lesser
 # General Public License Version 3 or the Perl Artistic License Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
@@ -11,7 +11,7 @@
 # Then 'make maintainer-dist'
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[5.042 2025-11-02],
+AC_INIT([Verilator],[5.044 2026-01-01],
         [https://verilator.org],
         [verilator],[https://verilator.org])
 
@@ -475,6 +475,7 @@ _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-shadow)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-unused-parameter)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Xclang -fno-pch-timestamp)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-faligned-new)
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-exceptions)
 AC_SUBST(CFG_CXXFLAGS_SRC)
 
 # Flags for compiling Verilator parser always (in addition to above CFG_CXXFLAGS_SRC)
@@ -533,7 +534,8 @@ m4_foreach([cflag],[
         [-Wno-unused-but-set-parameter],
         [-Wno-unused-but-set-variable],
         [-Wno-unused-parameter],
-        [-Wno-unused-variable]],[
+        [-Wno-unused-variable],
+        [-Wno-vla-cxx-extension]],[
     _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,cflag)
     # CMake will test what flags work itself, so pass all flags through to it
     CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE cflag"

docs/CONTRIBUTING.rst

@@ -23,8 +23,8 @@ Did you find a Verilator bug?
     demonstrating the bug and expected behavior that is not occurring.
 
   - The ideal example works against other simulators, and is in the
-    test_regress/t test format, as described in
+    test_regress/t test format, as described in `Verilator Internals
-    `Verilator Internals Documentation
+    Documentation
     <https://github.com/verilator/verilator/blob/master/docs/internals.rst>`__.
 
 
@@ -38,18 +38,18 @@ Did you write a patch that fixes a Verilator bug?
   <https://github.com/verilator/verilator/pulls>`__.
 
 - See the coding conventions, and other developer information in
-  ``docs/internals.rst`` in the distribution, or as rendered at
+  ``docs/internals.rst`` in the distribution, or as rendered at `Verilator
-  `Verilator Internals Documentation
+  Internals Documentation
   <https://github.com/verilator/verilator/blob/master/docs/internals.rst>`__.
 
-- Verilator uses GitHub Actions to provide continuous integration.  You
+- Verilator uses GitHub Actions to provide continuous integration. You may
-  may want to enable Actions on your GitHub branch to ensure your changes
+  want to enable Actions on your GitHub branch to ensure your changes keep
-  keep the tests passing.
+  the tests passing.
 
-- Your source-code contributions must be certified as open source,
+- Your source-code contributions must be certified as open source, under
-  under the `Developer Certificate of
+  the `Developer Certificate of Origin
-  Origin <https://developercertificate.org/>`__. On your first
+  <https://developercertificate.org/>`__. On your first contribution, you
-  contribution, you must either:
+  must either:
 
   - Have your patch include the addition of your name to `docs/CONTRIBUTORS
     <CONTRIBUTORS>`__ (preferred).
@@ -75,9 +75,9 @@ Did you write a patch that fixes a Verilator bug?
 Do you have questions on Verilator?
 -----------------------------------
 
-- Please see FAQ section and rest of the `Verilator
+- Please see FAQ section and rest of the `Verilator manual
-  manual <https://verilator.org/verilator_doc.html>`__, or `Verilator
+  <https://verilator.org/verilator_doc.html>`__, or `Verilator manual (PDF)
-  manual (PDF) <https://verilator.org/verilator_doc.pdf>`__.
+  <https://verilator.org/verilator_doc.pdf>`__.
 
 - Ask any question in the `Verilator forum
   <https://verilator.org/forum>`__.

docs/CONTRIBUTORS

@@ -38,7 +38,7 @@ Chuxuan Wang
 Chykon
 Congcong Cai
 Conor McCullough
-Dan Petrisko
+Dan Ruelas-Petrisko
 Daniel Bates
 Danny Oler
 Dave Sargeant
@@ -105,6 +105,8 @@ Jamey Hicks
 Jamie Iles
 Jan Van Winkel
 Jean Berniolles
+Jean-Nicolas Strauss
+Jens Yuechao Liu
 Jeremy Bennett
 Jesse Taube
 Jevin Sweval
@@ -123,6 +125,7 @@ John Wehle
 Jonathan Drolet
 Jonathan Schröter
 Jordan McConnon
+Jose Drowne
 Jose Loyola
 Josep Sans
 Joseph Nwabueze
@@ -190,6 +193,7 @@ Paul Bowen-Huggett
 Paul Swirhun
 Paul Wright
 Pawel Jewstafjew
+Pawel Kojma
 Pawel Sagan
 Pengcheng Xu
 Peter Birch
@@ -230,6 +234,8 @@ Steven Hugg
 Szymon Gizler
 Sören Tempel
 Teng Huang
+Thomas Aldrian
+Thomas Dybdahl Ahle
 Tim Hutt
 Tim Snyder
 Tobias Jensen
@@ -270,8 +276,10 @@ Zhen Yan
 Zhou Shen
 Zhouyi Shen
 Zixi Li
+apocelipes
 dependabot[bot]
 february cozzocrea
 sumpster
+em2machine
 Àlex Torregrosa
 Ícaro Lima

docs/Makefile

@@ -5,7 +5,7 @@
 #
 # Code available from: https://verilator.org
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2026 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.

docs/README.rst

@@ -10,8 +10,8 @@ For formatted documentation see:
 - `Verilator installation and package directory structure
   <https://verilator.org/install>`_
 
-- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_,
+- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or
-  or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
+  `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
 
 - `Subscribe to Verilator announcements
   <https://github.com/verilator/verilator-announce>`_

docs/bin/vl_sphinx_extract

@@ -37,7 +37,7 @@ parser = argparse.ArgumentParser(
     allow_abbrev=False,
     formatter_class=argparse.RawDescriptionHelpFormatter,
     description="""Read a file and extract documentation data.""",
-    epilog=""" Copyright 2021-2025 by Wilson Snyder.  This package is free software;
+    epilog=""" Copyright 2021-2026 by Wilson Snyder.  This package is free software;
 you can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

docs/bin/vl_sphinx_fix

@@ -52,7 +52,7 @@ parser = argparse.ArgumentParser(
     allow_abbrev=False,
     formatter_class=argparse.RawDescriptionHelpFormatter,
     description="""Post-process Sphinx HTML.""",
-    epilog=""" Copyright 2021-2025 by Wilson Snyder.  This package is free software;
+    epilog=""" Copyright 2021-2026 by Wilson Snyder.  This package is free software;
 you can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

docs/gen/ex_ASSIGNEQEXPR_faulty.rst

@@ -1,9 +1,8 @@
 .. comment: generated by t_lint_assigneqexpr_bad
 .. code-block:: sv
    :linenos:
-   :emphasize-lines: 3
 
-     assign d_o =  // Note = not == below
+       output logic c_o,
-         (
+       output logic d_o
-         c_o = 1  // <--- Warning: ASSIGNEQEXPR
+   );
-         ) ? 1 : (
+     assign c_o = (a_i != 0) ? 1 : 0;

docs/gen/ex_SUPERNFIRST_faulty.rst

@@ -0,0 +1,8 @@
+.. comment: generated by t_class_new_supernfirst_bad
+.. code-block:: sv
+   :linenos:
+   :emphasize-lines: 3
+
+     function new();
+       int x = $random();
+       super.new(build_coverage(x), x);  // <--- BAD, must be first statement

docs/gen/ex_SUPERNFIRST_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_class_new_supernfirst_bad
+.. code-block::
+
+   %Error-SUPERNFIRST: example.v:1:11 'super.new' must be first statement in a 'function new' (IEEE 1800-2023 8.15)

docs/guide/changes.rst

@@ -1,11 +1,12 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ****************
 Revision History
 ****************
 
-.. COMMENT above header must use ### so there is an extra level of headers
+..
+   COMMENT above header must use *** so there is an extra level of headers
    here so the index won't show the huge list of revisions when clicking on
    "Revision History" in the sidebar.
 

docs/guide/conf.py

@@ -1,7 +1,7 @@
 # pylint: disable=C0103,C0114,C0116,C0301,E0402,W0622
 #
 # Configuration file for Verilator's Sphinx documentation builder.
-# Copyright 2003-2025 by Wilson Snyder.
+# Copyright 2003-2026 by Wilson Snyder.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 # This file only contains overridden options. For a full list:

docs/guide/connecting.rst

@@ -1,7 +1,7 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Connecting:
+.. _connecting:
 
 ******************************
 Connecting to Verilated Models
@@ -11,7 +11,7 @@ Structure of the Verilated Model
 ================================
 
 Verilator outputs a :file:`{prefix}.h` header file which defines a class
-named :code:`{prefix}` which represents the generated model the user is
+named ``{prefix}`` which represents the generated model the user is
 supposed to instantiate. This model class defines the interface of the
 Verilated model.
 
@@ -32,74 +32,72 @@ model:
   equivalents.
 
 * Public top level module instances are exposed as pointers to allow access
-  to :code:`/* verilator public */` items.
+  to ``/* verilator public */`` items.
 
-* The root of the design hierarchy (as in SystemVerilog :code:`$root`) is
+* The root of the design hierarchy (as in SystemVerilog ``$root``) is
-  exposed via the :code:`rootp` member pointer to allow access to model
+  exposed via the ``rootp`` member pointer to allow access to model
-  internals, including :code:`/* verilator public_flat */` items.
+  internals, including ``/* verilator public_flat */`` items.
 
 
-.. _Porting from pre 4.210:
+.. _porting from pre 4.210:
 
 Model interface changes in version 4.210
-------------------------------------------
+----------------------------------------
 
 Starting from version 4.210, the model class is an interface object.
 
 Up until Verilator version 4.204 inclusive, the generated model class was
 also the instance of the top level instance in the design hierarchy (what
-you would refer to with :code:`$root` in SystemVerilog).  This meant that
+you would refer to with ``$root`` in SystemVerilog). This meant that all
-all internal variables that were implemented by Verilator in the root scope
+internal variables that were implemented by Verilator in the root scope
 were accessible as members of the model class itself. Note there were often
-many such variable due to module inlining, including
+many such variable due to module inlining, including ``/* verilator
-:code:`/* verilator public_flat */` items.
+public_flat */`` items.
 
 This means that user code that accesses internal signals in the model
-(likely including :code:`/* verilator public_flat */` signals, as they are
+(likely including ``/* verilator public_flat */`` signals, as they are
 often inlined into the root scope) will need to be updated as follows:
 
 * No change required for accessing top level IO signals. These are directly
   accessible in the model class via references.
 
-* No change required for accessing :code:`/* verilator public */` items.
+* No change required for accessing ``/* verilator public */`` items. These
-  These are directly accessible via sub-module pointers in the model class.
+  are directly accessible via sub-module pointers in the model class.
 
 * Accessing any other internal members, including
-  :code:`/* verilator public_flat */` items requires the following changes:
+  ``/* verilator public_flat */`` items requires the following changes:
 
   * Additionally include :file:`{prefix}___024root.h`. This header defines
-    type of the :code:`rootp` pointer within the model class. Note the
+    type of the ``rootp`` pointer within the model class. Note the
-    :code:`__024` substring is the Verilator escape sequence for the
+    ``__024`` substring is the Verilator escape sequence for the ``$``
-    :code:`$` character, i.e.: :code:`rootp` points to the Verilated
+    character, i.e.: ``rootp`` points to the Verilated SystemVerilog
-    SystemVerilog :code:`$root` scope.
+    ``$root`` scope.
 
-  * Replace :code:`modelp->internal->member` references with
+  * Replace ``modelp->internal->member`` references with
-    :code:`modelp->rootp->internal->member` references, which
+    ``modelp->rootp->internal->member`` references, which contain one
-    contain one additional indirection via the :code:`rootp` pointer.
+    additional indirection via the ``rootp`` pointer.
 
 
-.. _Connecting to C++:
+.. _connecting to c++:
 
 Connecting to C++
 =================
 
-In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is a
+In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is
-simple C++ class.  The user must write a C++ wrapper and main loop for the
+a simple C++ class. The user must write a C++ wrapper and main loop for the
 simulation, which instantiates the model class, and link with the Verilated
 model.
 
 Refer to ``examples/make_tracing_c`` in the distribution for a detailed
 commented example.
 
-Top level IO signals are read and written as members of the model.  You
+Top level IO signals are read and written as members of the model. You call
-call the model's :code:`eval()` method to evaluate the model.  When the
+the model's ``eval()`` method to evaluate the model. When the simulation is
-simulation is complete call the model's :code:`final()` method to execute
+complete call the model's ``final()`` method to execute any SystemVerilog
-any SystemVerilog final blocks, and complete any assertions. If using
+final blocks, and complete any assertions. If using :vlopt:`--timing`,
-:vlopt:`--timing`, there are two additional functions for checking if
+there are two additional functions for checking if there are any events
-there are any events pending in the simulation due to delays, and for
+pending in the simulation due to delays, and for retrieving the simulation
-retrieving the simulation time of the next delayed event. See
+time of the next delayed event. See :ref:`Evaluation Loop`.
-:ref:`Evaluation Loop`.
-
 
 
 Connecting to SystemC
@@ -112,8 +110,8 @@ netlist as an instantiation.
 The SC_MODULE gets the same pinout as the Verilog module, with the
 following type conversions: Pins of a single bit become bool. Pins 2-32
 bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or
-uint64_t's depending on the :vlopt:`--no-pins64` option.  Wider pins
+uint64_t's depending on the :vlopt:`--no-pins64` option. Wider pins become
-become sc_bv's.  (Uints simulate the fastest so are used where possible.)
+sc_bv's. (Uints simulate the fastest so are used where possible.)
 
 Model internals, including lower level sub-modules are not pure SystemC
 code. This is a feature, as using the SystemC pin interconnect scheme
@@ -129,24 +127,25 @@ to indicate and document those functions that are part of the Verilated
 public API.
 
 Process-Level Clone APIs
---------------------------
+------------------------
 
-Modern operating systems support process-level clone (a.k.a copying, forking)
+Modern operating systems support process-level clone (a.k.a copying,
-with system call interfaces in C/C++, e.g., :code:`fork()` in Linux.
+forking) with system call interfaces in C/C++, e.g., ``fork()`` in Linux.
 
 However, after cloning a parent process, some resources cannot be inherited
-in the child process. For example, in POSIX systems, when you fork a process,
+in the child process. For example, in POSIX systems, when you fork a
-the child process inherits all the memory of the parent process. However,
+process, the child process inherits all the memory of the parent process.
-only the thread that called fork is replicated in the child process. Other
+However, only the thread that called fork is replicated in the child
-threads are not.
+process. Other threads are not.
 
-Therefore, to support the process-level clone mechanisms, Verilator supports
+Therefore, to support the process-level clone mechanisms, Verilator
-:code:`prepareClone()` and :code:`atClone()` APIs to allow the user to manually
+supports ``prepareClone()`` and ``atClone()`` APIs to allow the user to
-re-construct the model in the child process. The two APIs handle all necessary
+manually re-construct the model in the child process. The two APIs handle
-resources required for releasing and re-initializing before and after cloning.
+all necessary resources required for releasing and re-initializing before
+and after cloning.
 
-The two APIs are supported in the verilated models. Here is an example of usage
+The two APIs are supported in the verilated models. Here is an example of
-with Linux :code:`fork()` and :code:`pthread_atfork` APIs:
+usage with Linux ``fork()`` and ``pthread_atfork`` APIs:
 
 .. code-block:: C++
 
@@ -158,7 +157,7 @@ with Linux :code:`fork()` and :code:`pthread_atfork` APIs:
    pthread_atfork(prepareClone, atClone, atClone);
 
 For better flexibility, you can also manually call the handlers before and
-after :code:`fork()`.
+after ``fork()``.
 
 With the process-level clone APIs, users can create process-level snapshots
 for the verilated models. While the Verilator save/restore option provides
@@ -243,8 +242,8 @@ From the sc_main.cpp file, you'd then:
    #include "Vour__Dpi.h"
    publicSetBool(value);
 
-Or, alternatively, call the function under the design class.  This isn't
+Or, alternatively, call the function under the design class. This isn't DPI
-DPI compatible but is easier to read and better supports multiple designs.
+compatible but is easier to read and better supports multiple designs.
 
 .. code-block:: C++
 
@@ -361,11 +360,10 @@ DPI Header Isolation
 Verilator places the IEEE standard header files such as svdpi.h into a
 separate include directory, vltstd (VeriLaTor STandarD). When compiling
 most applications $VERILATOR_ROOT/include/vltstd would be in the include
-path along with the normal $VERILATOR_ROOT/include.  However, when
+path along with the normal $VERILATOR_ROOT/include. However, when compiling
-compiling Verilated models into other simulators which have their own
+Verilated models into other simulators which have their own svdpi.h and
-svdpi.h and similar standard files with different contents, the vltstd
+similar standard files with different contents, the vltstd directory should
-directory should not be included to prevent picking up incompatible
+not be included to prevent picking up incompatible definitions.
-definitions.
 
 
 Public Functions
@@ -390,12 +388,11 @@ documented below.
 
 Verilator has an important difference from an event based simulator; signal
 values that are changed by the VPI will not immediately propagate their
-values, instead the top level header file's :code:`eval()` method must be
+values, instead the top level header file's ``eval()`` method must be
-called.  Normally this would be part of the normal evaluation (i.e. the
+called. Normally this would be part of the normal evaluation (i.e. the next
-next clock edge), not as part of the value change.  This makes the
+clock edge), not as part of the value change. This makes the performance of
-performance of VPI routines extremely fast compared to event based
+VPI routines extremely fast compared to event based simulators, but can
-simulators, but can confuse some test-benches that expect immediate
+confuse some test-benches that expect immediate propagation.
-propagation.
 
 Note the VPI by its specified implementation will always be much slower
 than accessing the Verilator values by direct reference
@@ -405,27 +402,28 @@ while the direct references are evaluated by the compiler and result in
 only a couple of instructions.
 
 For signal callbacks to work the main loop of the program must call
-:code:`VerilatedVpi::callValueCbs()`.
+``VerilatedVpi::callValueCbs()``.
 
-Verilator also tracks when the model state has been modified via the VPI with
+Verilator also tracks when the model state has been modified via the VPI
-an :code:`evalNeeded` flag.  This flag can be checked with :code:`VerilatedVpi::evalNeeded()`
+with an ``evalNeeded`` flag. This flag can be checked with
-and it can be cleared with :code:`VerilatedVpi::clearEvalNeeded()`.  Used together
+``VerilatedVpi::evalNeeded()`` and it can be cleared with
-it is possible to skip :code:`eval()` calls if no model state has been changed
+``VerilatedVpi::clearEvalNeeded()``. Used together it is possible to skip
-since the last :code:`eval()`.
+``eval()`` calls if no model state has been changed since the last
+``eval()``.
 
-Any data written via :code:`vpi_put_value` with :code:`vpiInertialDelay` will
+Any data written via ``vpi_put_value`` with ``vpiInertialDelay`` will be
-be deferred for later.  These delayed values can be flushed to the model with
+deferred for later. These delayed values can be flushed to the model with
-:code:`VerilatedVpi::doInertialPuts()`.
+``VerilatedVpi::doInertialPuts()``.
 
 
-.. _VPI Example:
+.. _vpi example:
 
 VPI Example
 -----------
 
 In the below example, we have readme marked read-only, and writeme marked
-read-write which if written from outside the model will have the same semantics
+read-write which if written from outside the model will have the same
-as if it was a top level input.
+semantics as if it was a top level input.
 
 .. code-block:: bash
 
@@ -482,55 +480,53 @@ accesses the above signal "readme" would be:
    EOF
 
 
-.. _Evaluation Loop:
+.. _evaluation loop:
 
 Wrappers and Model Evaluation Loop
 ==================================
 
 When using SystemC, evaluation of the Verilated model is managed by the
 SystemC kernel, and for the most part can be ignored. When using C++, the
-user must call :code:`eval()`, or :code:`eval_step()` and
+user must call ``eval()``, or ``eval_step()`` and ``eval_end_step()``.
-:code:`eval_end_step()`.
 
 1. When there is a single design instantiated at the C++ level that needs
-to evaluate within a given context, call :code:`designp->eval()`.
+to evaluate within a given context, call ``designp->eval()``.
 
 2. When there are multiple designs instantiated at the C++ level that need
-to evaluate within a context, call :code:`first_designp->eval_step()` then
+to evaluate within a context, call ``first_designp->eval_step()`` then
-:code:`->eval_step()` on all other designs.  Then call
+``->eval_step()`` on all other designs. Then call ``->eval_end_step()`` on
-:code:`->eval_end_step()` on the first design then all other designs.  If
+the first design then all other designs. If there is only a single design,
-there is only a single design, you would call :code:`eval_step()` then
+you would call ``eval_step()`` then ``eval_end_step()``; in fact ``eval()``
-:code:`eval_end_step()`; in fact :code:`eval()` described above is just a
+described above is just a wrapper which calls these two functions.
-wrapper which calls these two functions.
 
 3. If using delays and :vlopt:`--timing`, there are two additional methods
 the user should call:
 
-   * :code:`designp->eventsPending()`, which returns :code:`true` if there are
+   * ``designp->eventsPending()``, which returns ``true`` if there are any
-     any delayed events pending,
+     delayed events pending,
-   * :code:`designp->nextTimeSlot()`, which returns the simulation time of the
+   * ``designp->nextTimeSlot()``, which returns the simulation time of the
      next delayed event. This method can only be called if
-     :code:`designp->eventsPending()` returned :code:`true`.
+     ``designp->eventsPending()`` returned ``true``.
 
-Call :code:`eventsPending()` to check if you should continue with the
+Call ``eventsPending()`` to check if you should continue with the
-simulation, and then :code:`nextTimeSlot()` to move simulation time forward.
+simulation, and then ``nextTimeSlot()`` to move simulation time forward.
-:vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic example
+:vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic
-of a timing-enabled eval loop.
+example of a timing-enabled eval loop.
 
-When :code:`eval()` (or :code:`eval_step()`) is called Verilator looks for
+When ``eval()`` (or ``eval_step()``) is called Verilator looks for changes
-changes in clock signals and evaluates related sequential always blocks,
+in clock signals and evaluates related sequential always blocks, such as
-such as computing always_ff @ (posedge...) outputs. With :vlopt:`--timing`, it
+computing always_ff @ (posedge...) outputs. With :vlopt:`--timing`, it
 resumes any delayed processes awaiting the current simulation time. Then
 Verilator evaluates combinational logic.
 
 Note combinatorial logic is not computed before sequential always blocks
 are computed (for speed reasons). Therefore it is best to set any non-clock
-inputs up with a separate :code:`eval()` call before changing clocks.
+inputs up with a separate ``eval()`` call before changing clocks.
 
 Alternatively, if all always_ff statements use only the posedge of clocks,
 or all inputs go directly to always_ff statements, as is typical, then you
 can change non-clock inputs on the negative edge of the input clock, which
-will be faster as there will be fewer :code:`eval()` calls.
+will be faster as there will be fewer ``eval()`` calls.
 
 For more information on evaluation, see :file:`docs/internals.rst` in the
 distribution.
@@ -548,10 +544,10 @@ using only the single, default VerilatedContext.
 
 The ``Verilated::`` methods, including the ``Verilated::commandArgs`` call
 shown above, call VerilatedContext methods using the default global
-VerilatedContext.  (Technically they operate on the last one used by a
+VerilatedContext. (Technically they operate on the last one used by a given
-given thread.)  If you are using multiple simulation contexts you should
+thread.) If you are using multiple simulation contexts you should not use
-not use the Verilated:: methods, and instead always use VerilatedContext
+the Verilated:: methods, and instead always use VerilatedContext methods
-methods called on the appropriate VerilatedContext object.
+called on the appropriate VerilatedContext object.
 
 For methods available under Verilated and VerilatedContext see
 :file:`include/verilated.h` in the distribution.

docs/guide/contributing.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *******************************
@@ -19,12 +19,12 @@ Reporting Bugs
 
 First, check the :ref:`Language Limitations` section.
 
-Next, try the :vlopt:`--debug` option.  This will enable additional
+Next, try the :vlopt:`--debug` option. This will enable additional internal
-internal assertions, and may help identify the problem.
+assertions, and may help identify the problem.
 
 Finally, reduce your code to the smallest possible routine that exhibits
-the bug (see: :ref:`Minimizing bug-inducing code`).  Even better, create
+the bug (see: :ref:`Minimizing bug-inducing code`). Even better, create a
-a test in the :file:`test_regress/t` directory, as follows:
+test in the :file:`test_regress/t` directory, as follows:
 
 .. code-block:: bash
 
@@ -62,7 +62,7 @@ Finally, report the bug at `Verilator Issues
 <https://verilator.org/issues>`_. The bug will become publicly visible; if
 this is unacceptable, mail the bug report to ``wsnyder@wsnyder.org``.
 
-.. _Minimizing bug-inducing code:
+.. _minimizing bug-inducing code:
 
 Minimizing bug-inducing code
 ============================
@@ -73,12 +73,12 @@ caused by a complex interaction of many parts of the design, and it is not
 clear which parts are necessary to reproduce the bug. In these cases, an
 Open Source tool called `sv-bugpoint
 <https://github.com/antmicro/sv-bugpoint>`_ can be used to automatically
-reduce a SystemVerilog design to the smallest possible reproducer.
+reduce a SystemVerilog design to the smallest possible reproducer. It can
-It can be used to automatically reduce a design with hundreds of thousands of
+be used to automatically reduce a design with hundreds of thousands of
 lines to a minimal test case while preserving the bug-inducing behavior.
 
 With :vlopt:`--debug` or :vlopt:`--dump-inputs`, Verilator will write a
-*{prefix}*\ __inputs\ .vpp file which has all of the individual input files
+*{prefix}*\ __inputs.vpp file which has all of the individual input files
 combined and pre-processed, this is often useful as the input design into
 `sv-bugpoint`.
 
@@ -88,4 +88,5 @@ information on how to use `sv-bugpoint`.
 
 .. Contributing
 .. ============
+
 .. include:: ../CONTRIBUTING.rst

docs/guide/contributors.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ************************
@@ -28,10 +28,11 @@ Alliance <https://chipsalliance.org>`_, and `Antmicro Ltd
 
 Previous major corporate sponsors of Verilator, by providing significant
 contributions of time or funds include: Antmicro Ltd., Atmel Corporation,
-Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Hicamp
+Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Fractile
-Systems, Intel Corporation, Marvell Inc., Mindspeed Technologies Inc.,
+Ltd., Hicamp Systems, Intel Corporation, Marvell Inc., Mindspeed
-MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus
+Technologies Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems
-Networks Inc., SiCortex Inc, Shunyao CAD, and Western Digital Inc.
+Inc., Nauticus Networks Inc., SiCortex Inc, Shunyao CAD, and Western
+Digital Inc.
 
 The contributors of major functionality are: Jeremy Bennett, Krzysztof
 Bieganski, Byron Bradley, Lane Brooks, John Coiner, Duane Galbi, Arkadiusz
@@ -41,133 +42,158 @@ Paul Wasson, Jie Xu, and Wilson Snyder.
 Some of the people who have provided ideas, and feedback for Verilator
 include:
 
-David Addison, Tariq B. Ahmad, Nikana Anastasiadis, John David Anglin,
+Gilberto Abram, David Addison, Joey Ah-kiow, Thomas Dybdahl Ahle, Tariq B.
-Frederic Antonin, Hans Van Antwerpen, Vasu Arasanipalai, Jens Arm, Rohan
+Ahmad, Thomas Aldrian, Omar Alkhatib, Amal Araweelo Almis, Nikana
-Arshid, Valentin Atepalikhin, Philip Axer, Gökçe Aydos, Chris Bachhuber,
+Anastasiadis, John David Anglin, Frederic Antonin, Hans Van Antwerpen, Vasu
-Filip Badáň, Adam Bagley, Sharad Bagri, James Bailey, Robert Balas, Marco
+Arasanipalai, Jens Arm, Rohan Arshid, Valentin Atepalikhin, Philip Axer,
-Balboni, Matthew Ballance, Ricardo Barbedo, Andrew Bardsley, Ilya Barkov,
+Gökçe Aydos, Chris Bachhuber, Filip Badáň, Adam Bagley, Sharad Bagri, James
-Matthew Barr, Geoff Barrett, Kaleb Barrett, Daniel Bates, Julius Baxter,
+Bailey, Robert Balas, Marco Balboni, Matthew Ballance, Ricardo Barbedo,
-Michael Berman, Jean Berniolles, Victor Besyakov, Narayan Bhagavatula,
+Andrew Bardsley, Ilya Barkov, Matthew Barr, Geoff Barrett, Kaleb Barrett,
-Moinak Bhattacharyya, Kritik Bhimani, David Biancolin, Krzysztof Bieganski,
+Daniel Bates, Julius Baxter, Jeremy Bennett, Michael Berman, Jean
-Michael Bikovitsky, David Binderman, Piotr Binkowski, Johan Björk, David
+Berniolles, Victor Besyakov, Narayan Bhagavatula, Moinak Bhattacharyya,
-Black, Tymoteusz Blazejczyk, Scott Bleiweiss, David van der Bokke, Daniel
+Kritik Bhimani, David Biancolin, Krzysztof Bieganski, Artur Bieniek,
-Bone, Guy Bonneau, Krzysztof Boroński, Gregg Bouchard, Christopher
+Michael Bikovitsky, David Binderman, Piotr Binkowski, Peter Birch, Johan
-Boumenot, Paul Bowen-Huggett, Nick Bowler, Bryan Brady, Maarten De
+Björk, David Black, Tymoteusz Blazejczyk, Scott Bleiweiss, Joel Bodenmann,
-Braekeleer, Liam Braun, Charlie Brej, J Briquet, John Brownlee, KC
+David van der Bokke, Daniel Bone, Guy Bonneau, Pierre-Yves Le Borgne,
-Buckenmaier, Gijs Burghoorn, Jeff Bush, Lawrence Butcher, Tony Bybell, Iru
+Krzysztof Boroński, Gregg Bouchard, Christopher Boumenot, Paul
-Cai, Ted Campbell, Anthony Campos, Chris Candler, Lauren Carlson, Gregory
+Bowen-Huggett, Nick Bowler, Byron Bradley, Bryan Brady, Maarten De
-Carver, Donal Casey, Sebastien Van Cauwenberghe, Alex Chadwick, Greg
+Braekeleer, Liam Braun, Charlie Brej, Nick Brereton, J Briquet, Lane
-Chadwick, Marcel Chang, Aliaksei Chapyzhenka, Chih-Mao Chen, Guokai Chen,
+Brooks, John Brownlee, KC Buckenmaier, Gijs Burghoorn, Jeff Bush, Lawrence
-Kefa Chen, Terry Chen, Yangyu Chen, Yi-Chung Chen, Yurii Cherkasov,
+Butcher, Tony Bybell, Congcong Cai, Iru Cai, Ted Campbell, Anthony Campos,
-Hennadii Chernyshchyk, Enzo Chi, Bartłomiej Chmiel, Robert A. Clark, Ryan
+Chris Candler, Lauren Carlson, Gregory Carver, Donal Casey, Sebastien Van
-Clarke, Allan Cochrane, Keith Colbert, Quentin Corradi, Nassim Corteggiani,
+Cauwenberghe, Alex Chadwick, Greg Chadwick, Marcel Chang, Aliaksei
-Gianfranco Costamagna, February Cozzocrea, Sean Cross, George Cuan, Michal
+Chapyzhenka, Chih-Mao Chen, Guokai Chen, Kefa Chen, Terry Chen, Yangyu
-Czyz, Joe DErrico, Jim Dai, Lukasz Dalek, Laurens van Dam, Gunter
+Chen, Yi-Chung Chen, Yurii Cherkasov, Hennadii Chernyshchyk, Enzo Chi,
-Dannoritzer, Ashutosh Das, Julian Daube, Greg Davill, Bernard Deadman,
+Bartłomiej Chmiel, Sergey Chusov, Robert A. Clark, Ryan Clarke, Allan
-Peter Debacker, Josse Van Delm, John Demme, Mike Denio, John Deroo, Philip
+Cochrane, John Coiner, Luca Colagrande, Keith Colbert, Quentin Corradi,
-Derrick, Aadi Desai, John Dickol, Ruben Diez, Danny Ding, Jacko Dirks, Ivan
+Nassim Corteggiani, Gianfranco Costamagna, February Cozzocrea, Sean Cross,
-Djordjevic, Brad Dobbie, Paul Donahue, Jonathon Donaldson, Anthony Donlon,
+George Cuan, RJ Cunningham, Michal Czyz, Joe DErrico, Jim Dai, Lukasz
-Caleb Donovick, Larry Doolittle, Leendert van Doorn, Sebastian Dressler,
+Dalek, Laurens van Dam, Gunter Dannoritzer, Ashutosh Das, Julian Daube,
-Jonathan Drolet, Justin Yao Du, Maciej Dudek, Alex Duller, Jeff Dutton,
+Greg Davill, Bernard Deadman, Peter Debacker, Josse Van Delm, John Demme,
-Tomas Dzetkulic, Usuario Eda, Charles Eddleston, Chandan Egbert, Joe Eiler,
+Mike Denio, John Deroo, Philip Derrick, Aadi Desai, John Dickol, Ruben
-Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Robert Farrell, Julien
+Diez, Danny Ding, Jacko Dirks, Ivan Djordjevic, Brad Dobbie, Paul Donahue,
-Faucher, Olivier Faure, Eugene Feinberg, Eugen Fekete, Fabrizio Ferrandi,
+Jonathon Donaldson, Anthony Donlon, Caleb Donovick, Larry Doolittle,
-Udi Finkelstein, Brian Flachs, Bill Flynn, Andrea Foletto, Alex Forencich,
+Leendert van Doorn, Sebastian Dressler, Connor Driscoll, Jonathan Drolet,
-Aurelien Francillon, Bob Fredieu, Manuel Freiberger, Mostafa Gamal, Vito
+Jose Drowne, Justin Yao Du, Maciej Dudek, Alex Duller, Jeff Dutton, Tomas
-Gamberini, Mostafa Garnal, Benjamin Gartner, Christian Gelinek, Richard E
+Dzetkulic, Usuario Eda, Charles Eddleston, Chandan Egbert, Joe Eiler, Ahmed
-George, Peter Gerst, Glen Gibb, Michael Gielda, Barbara Gigerl, Nimrod
+El-Mahmoudy, Trevor Elbourne, Schuyler Eldridge, Ahmed Elzeftawi, Mats
-Gileadi, Shankar Giri, Dan Gisselquist, Szymon Gizler, Petr Gladkikh, Sam
+Engstrom, Augustin Fabre, Robert Farrell, Julien Faucher, Olivier Faure,
-Gladstone, Mariusz Glebocki, Embedded Go, Andrew Goessling, Amir Gonnen,
+Sergey Fedorov, Eugene Feinberg, Eugen Fekete, Fabrizio Ferrandi, Adrian
-Chitlesh Goorah, Tomasz Gorochowik, Kai Gossner, Tarik Graba, Sergi
+Fiergolski, Udi Finkelstein, Brian Flachs, Bill Flynn, Andrea Foletto,
-Granell, Al Grant, Nathan Graybeal, Alexander Grobman, Qian Gu, Xuan Guo,
+Maxim Fonarev, Alex Forencich, Aurelien Francillon, Marco Frank, Bob
-Prabhat Gupta, Deniz Güzel, Driss Hafdi, Abdul Hameed, Neil Hamilton, James
+Fredieu, Manuel Freiberger, Stephane Gagnon, Duane Galbi, Mostafa Gamal,
-Hanlon, Tang Haojin, Øyvind Harboe, Jannis Harder, David Harris, Junji
+Vito Gamberini, Mateusz Gancarz, Mostafa Garnal, Benjamin Gartner,
-Hashimoto, Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry,
+Christian Gelinek, Richard E George, Peter Gerst, Glen Gibb, Michael
-Stephen Henry, Sebastian Hesselbarth, David Hewson, Jamey Hicks, Joel
+Gielda, Barbara Gigerl, Nimrod Gileadi, Shankar Giri, Dan Gisselquist,
-Holdsworth, Andrew Holme, Peter Holmes, Hiroki Honda, Alex Hornung,
+Szymon Gizler, Petr Gladkikh, Sam Gladstone, Mariusz Glebocki, Embedded Go,
-Pierre-Henri Horrein, David Horton, Peter Horvath, Jae Hossell, Kuoping
+Andrew Goessling, Emil Goh, Amir Gonnen, Chitlesh Goorah, Tomasz
-Hsu, Shou-Li Hsu, Teng Huang, Steven Hugg, Alan Hunter, James Hutchinson,
+Gorochowik, Kai Gossner, Toshiki Goto, Tarik Graba, Sergi Granell, Al
-Tim Hutt, Ehab Ibrahim, Edgar E. Iglesias, Shahid Ikram, Jamie Iles, Fuad
+Grant, Nathan Graybeal, Alexander Grobman, Dominick Grochowina, Qian Gu,
-Ismail, Vighnesh Iyer, Ben Jackson, Daniel Jacques, Shareef Jalloq, Marlon
+Karol Gugala, Xuan Guo, Prabhat Gupta, Oscar Gustafsson, Deniz Güzel, Driss
-James, Krzysztof Jankowski, Eyck Jentzsch, HyungKi Jeong, Iztok Jeras,
+Hafdi, Abdul Hameed, Neil Hamilton, Ali Hammoud, James Hanlon, Tang Haojin,
-Pawel Jewstafjew, Alexandre Joannou, James Johnson, Christophe Joly, Justin
+Øyvind Harboe, Jannis Harder, David Harris, Junji Hashimoto, Thomas
-Jones, William D. Jones, Abe Jordan, Larry Darryl Lee Jr., Franck Jullien,
+Hawkins, Mitch Hayenga, Christian Hecken, Harald Heckmann, Robin Heinemann,
-James Jung, Mike Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje,
+Robert Henry, Stephen Henry, Sebastian Hesselbarth, David Hewson, Jamey
-Vasu Kandadi, Yoshitomo Kaneda, Kanad Kanhere, Patricio Kaplan, Pieter
+Hicks, Joel Holdsworth, Andrew Holme, Peter Holmes, Hiroki Honda, Steve
-Kapsenberg, Rafal Kapuscik, Ralf Karge, Per Karlsson, Dan Katz, Sol
+Hoover, Alex Hornung, Pierre-Henri Horrein, David Horton, Peter Horvath,
-Katzman, Ian Kennedy, Ami Keren, Fabian Keßler, Michael Killough, Sun Kim,
+Jae Hossell, Kuoping Hsu, Shou-Li Hsu, Teng Huang, Steven Hugg, Alan
-Jonathan Kimmitt, Olof Kindgren, Kevin Kiningham, Cameron Kirk, Dan
+Hunter, James Hutchinson, Tim Hutt, Ehab Ibrahim, Edgar E. Iglesias, Shahid
-Kirkham, Aleksander Kiryk, Sobhan Klnv, Gernot Koch, Jack Koenig, Soon Koh,
+Ikram, Jamie Iles, Ondrej Ille, Ron K. Irvine, Fuad Ismail, Vighnesh Iyer,
-Nathan Kohagen, Steve Kolecki, Brett Koonce, Will Korteland, Andrei
+Ben Jackson, Daniel Jacques, Shareef Jalloq, Marlon James, Krzysztof
-Kostovski, Wojciech Koszek, Varun Koyyalagunta, Arkadiusz Kozdra, Markus
+Jankowski, Moubarak Jeje, Tobias Jensen, Eyck Jentzsch, HyungKi Jeong,
-Krause, David Kravitz, Adam Krolnik, Roland Kruse, Mahesh Kumashikar,
+Iztok Jeras, Pawel Jewstafjew, Aditya Ranjan Jha, Xie Jiacheng, Alexandre
-Andreas Kuster, Sergey Kvachonok, Charles Eric LaForest, Kevin Laeufer, Ed
+Joannou, James Johnson, Christophe Joly, Justin Jones, William D. Jones,
-Lander, Steve Lang, Pierre Laroche, Stephane Laurent, Walter Lavino,
+Kees Jongenburger, Abe Jordan, Larry Darryl Lee Jr., Franck Jullien, James
-Christian Leber, David Ledger, Alex Lee, Larry Lee, Yoda Lee, Michaël
+Jung, Yoshitomo KANEDA, Mike Kagen, Arthur Kahlich, Kaalia Kahn, G-A.
-Lefebvre, Dag Lem, Igor Lesik, John Li, Kay Li, Zixi Li, Davide Libenzi,
+Kamendje, Guy-Armand Kamendje, Vasu Kandadi, Kanad Kanhere, Patricio
-Nandor Licker, Eivind Liland, Ícaro Lima, Kevin Lin, Yu-Sheng Lin, Charlie
+Kaplan, Pieter Kapsenberg, Rafal Kapuscik, Ralf Karge, Per Karlsson, Dan
-Lind, Andrew Ling, Jiuyang Liu, Joey Liu, Paul Liu, Derek Lockhart, Jake
+Katz, Sol Katzman, Amirreza Kazemi, Ian Kennedy, Ami Keren, Fabian
-Longo, Geza Lore, Arthur Low, Jose Loyola, Stefan Ludwig, Dan Lussier,
+Keßler-Schulz, John Khoo, Michael Killough, Sun Kim, Jonathan Kimmitt, Olof
-Konstantin Lübeck, Fred Ma, Liwei Ma, Duraid Madina, Oleh Maksymenko, Affe
+Kindgren, Kevin Kiningham, Cameron Kirk, Dan Kirkham, Aleksander Kiryk,
-Mao, Julien Margetts, Chick Markley, Alexis Marquet, Mark Marshall, Alfonso
+Sobhan Klnv, Gernot Koch, Jack Koenig, Soon Koh, Nathan Kohagen, Pawel
-Martinez, Unai Martinez-Corral, Adrien Le Masle, Yves Mathieu, Vladimir
+Kojma, Steve Kolecki, Brett Koonce, Will Korteland, Andrei Kostovski,
-Matveyenko, Patrick Maupin, Stan Mayer, Jordan McConnon, Conor McCullough,
+Wojciech Koszek, Varun Koyyalagunta, Arkadiusz Kozdra, Markus Krause, David
-Jason McMullan, Elliot Mednick, Yuan Mei, Andy Meier, Luiza de Melo,
+Kravitz, Natan Kreimer, Adam Krolnik, Roland Kruse, Jan Kubalek, Mahesh
-Rodrigo A. Melo, Benjamin Menküc, Jake Merdich, David Metz, Wim Michiels,
+Kumashikar, Andreas Kuster, Sergey Kvachonok, Charles Eric LaForest, Kevin
+Laeufer, Ed Lander, Steve Lang, Pierre Laroche, Stephane Laurent, Walter
+Lavino, Christian Leber, David Ledger, Alex Lee, Larry Lee, Yoda Lee,
+Michaël Lefebvre, Dag Lem, Igor Lesik, Brian Li, John Li, Kay Li, Zixi Li,
+Davide Libenzi, Matt Liberty, Nandor Licker, Eivind Liland, Ícaro Lima,
+Jian Nan Lin, Kevin Lin, Yu-Sheng Lin, Charlie Lind, Andrew Ling, Jens
+Yuechao Liu, Jiuyang Liu, Joey Liu, Paul Liu, Derek Lockhart, Jake Longo,
+Geza Lore, Arthur Low, Jose Loyola, Stefan Ludwig, Martin Lueker-Boden, Dan
+Lussier, Konstantin Lübeck, Fred Ma, Liwei Ma, Duraid Madina, Oleh
+Maksymenko, Alexander Mann, Affe Mao, Rémi Marche, Julien Margetts, Chick
+Markley, Alexis Marquet, Mark Marshall, Alfonso Martinez, Unai
+Martinez-Corral, Adrien Le Masle, Yves Mathieu, Vladimir Matveyenko,
+Patrick Maupin, Stan Mayer, Jordan McConnon, Conor McCullough, Jason
+McMullan, Elliot Mednick, Yuan Mei, Andy Meier, Luiza de Melo, Rodrigo A.
+Melo, Benjamin Menküc, Niraj Menon, Jake Merdich, David Metz, Wim Michiels,
 Miodrag Milanović, Darryl Miles, Kevin Millis, Andrew Miloradovsky, David
-Moberg, Wai Sum Mong, Peter Monsson, Anthony Moore, Sean Moore, Stuart
+Moberg, Wai Sum Mong, Peter Monsson, Anthony Moore, Sean Moore, Javier
-Morris, Dennis Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard
+Mora, Rodrigo Batista de Moraes, Stuart Morris, Dennis Muhlestein, John
-Myers, Alex Mykyta, Eric Müller, Dimitris Nalbantis, Peter Nelson, Felix
+Murphy, Matt Myers, Nathan Myers, Richard Myers, Alex Mykyta, Shivaram
-Neumärker, Bob Newgard, Cong Van Nguyen, Rachit Nigam, Toru Niina, Paul
+Mysore, Eric Müller, Dimitris Nalbantis, Jitesh Nayak, Peter Nelson, Yuri
-Nitza, Yossi Nivin, Pete Nixon, Lisa Noack, Mark Nodine, Michael Nolan,
+Nenakhov, Felix Neumärker, Bob Newgard, Cong Van Nguyen, Trung Nguyen,
-Andrew Nolte, Joseph Nwabueze, Kevin Nygaard, Kuba Ober, Krzysztof
+Rachit Nigam, Toru Niina, Paul Nitza, Yossi Nivin, Pete Nixon, Lisa Noack,
-Obłonczek, Andreas Olofsson, Baltazar Ortiz, Aleksander Osman, Don Owen,
+Mark Nodine, Petr Nohavica, Michael Nolan, Andrew Nolte, Mateusz
-Tim Paine, Deepa Palaniappan, James Pallister, Vassilis Papaefstathiou,
+Nurczyński, Joseph Nwabueze, Kevin Nygaard, Thomas O'Keeffe, Kuba Ober,
-Sanggyu Park, Brad Parker, Risto Pejašinović, Seth Pellegrino, Morten Borup
+Krzysztof Obłonczek, Danny Oler, Andreas Olofsson, Baltazar Ortiz,
-Petersen, Dan Petrisko, Wesley Piard, Maciej Piechotka, David Pierce, Cody
+Aleksander Osman, Don Owen, Tim Paine, Deepa Palaniappan, James Pallister,
-Piersall, T. Platz, Michael Platzer, Dominic Plunkett, Nolan Poe, David
+Vassilis Papaefstathiou, Sanggyu Park, Brad Parker, Risto Pejašinović, Seth
-Poole, Michael Popoloski, Roman Popov, Aylon Chaim Porat, Oron Port, Rich
+Pellegrino, Joel Peltonen, Morten Borup Petersen, Dan Petrisko, Thanh Tung
-Porter, Rick Porter, Stefan Post, Niranjan Prabhu, Damien Pretet, Harald
+Pham, Wesley Piard, Maciej Piechotka, David Pierce, Cody Piersall,
-Pretl, Bill Pringlemeir, Usha Priyadharshini, Mark Jackson Pulver, Prateek
+T. Platz, Michael Platzer, Dominic Plunkett, Nolan Poe, Tuomas Poikela,
-Puri, Han Qi, Jiacheng Qian, Marshal Qiao, Raynard Qiao, Yujia Qiao, Jasen
+George Polack, David Poole, Michael Popoloski, Roman Popov, Aylon Chaim
-Qin, Frank Qiu, Nandu Raj, Kamil Rakoczy, Danilo Ramos, Drew Ranck, Chris
+Porat, Oron Port, Rich Porter, Rick Porter, Stefan Post, Niranjan Prabhu,
-Randall, Anton Rapp, Josh Redford, Odd Magne Reitan, Frédéric Requin,
+Damien Pretet, Harald Pretl, Bill Pringlemeir, Usha Priyadharshini, Mark
-Dustin Richmond, Samuel Riedel, Alberto Del Rio, Eric Rippey, Narcis Rodas,
+Jackson Pulver, Prateek Puri, Nikolay Puzanov, Han Qi, Jiacheng Qian,
-Oleg Rodionov, Ludwig Rogiers, Paul Rolfe, Michail Rontionov, Arjen
+Marshal Qiao, Raynard Qiao, Yujia Qiao, Jasen Qin, Frank Qiu, Nandu Raj,
-Roodselaar, Arthur Rosa, Tobias Rosenkranz, Yernagula Roshit, Ryszard
+Kamil Rakoczy, Danilo Ramos, Drew Ranck, Chris Randall, Anton Rapp, Josh
-Rozak, Huang Rui, Graham Rushton, Jan Egil Ruud, Denis Rystsov, Pawel
+Redford, Odd Magne Reitan, Frédéric Requin, Wajahat Riaz, Dustin Richmond,
-Sagan, Robert Sammelson, Adrian Sampson, John Sanguinetti, Josep Sans, Luca
+Samuel Riedel, Alberto Del Rio, Eric Rippey, Narcis Rodas, Oleg Rodionov,
-Sasselli, Martin Scharrer, Martin Schmidt, Jonathan Schröter, Julie
+Ludwig Rogiers, Paul Rolfe, Michail Rontionov, Arjen Roodselaar, Arthur
+Rosa, Tobias Rosenkranz, Yernagula Roshit, Diego Roux, Ryszard Rozak, Dan
+Ruelas-Petrisko, Luca Rufer, Huang Rui, Graham Rushton, Jan Egil Ruud,
+Denis Rystsov, Pawel Sagan, Robert Sammelson, Adrian Sampson, John
+Sanguinetti, Josep Sans, Dave Sargeant, Luca Sasselli, Philippe Sauter,
+Martin Scharrer, Parker Schless, Martin Schmidt, Jonathan Schröter, Julie
 Schwartz, Galen Seitz, Sam Shahrestani, Joseph Shaker, Mark Shaw, Salman
-Sheikh, Zhou Shen, Hao Shi, James Shi, Michael Shinkarovsky, Rafael
+Sheikh, Zhou Shen, Zhouyi Shen, Hao Shi, James Shi, Michael Shinkarovsky,
-Shirakawa, Jeffrey Short, S Shuba, Fan Shupei, Ethan Sifferman, Anderson
+Rafael Shirakawa, Jeffrey Short, S Shuba, Fan Shupei, Ethan Sifferman,
-Ignacio da Silva, Rodney Sinclair, Ameya Vikram Singh, Sanjay Singh, Frans
+Anderson Ignacio da Silva, Rodney Sinclair, Ameya Vikram Singh, Sanjay
-Skarman, Nate Slager, Steven Slatter, Mladen Slijepcevic, Brian Small,
+Singh, Frans Skarman, Nate Slager, Steven Slatter, Mladen Slijepcevic,
-Garrett Smith, Gus Smith, Tim Snyder, Maciej Sobkowski, Stan Sokorac, Alex
+Brian Small, Garrett Smith, Gus Smith, Rachel Smith, Tim Snyder, Maciej
-Solomatnikov, Flavien Solt, Wei Song, Trefor Southwell, Martin Stadler, Art
+Sobkowski, Stan Sokorac, Alex Solomatnikov, Flavien Solt, Wei Song, Trefor
-Stamness, David Stanford, Krzysztof Starecki, Baruch Sterin, John
+Southwell, Martin Stadler, Art Stamness, David Stanford, Krzysztof
-Stevenson, Pete Stevenson, Patrick Stewart, Rob Stoddard, Tood Strader,
+Starecki, Baruch Sterin, John Stevenson, Pete Stevenson, Patrick Stewart,
-John Stroebel, Ray Strouble, Sven Stucki, Howard Su, Udaya Raj Subedi,
+Rob Stoddard, Tood Strader, Jean-Nicolas Strauss, John Stroebel, Ray
-Emerson Suguimoto, Gene Sullivan, Qingyao Sun, Renga Sundararajan, Kuba
+Strouble, Matt Stroud, Sven Stucki, Howard Su, Udaya Raj Subedi, Emerson
+Suguimoto, Gene Sullivan, Qingyao Sun, Renga Sundararajan, Kuba
 Sunderland-Ober, Gustav Svensk, Rupert Swarbrick, Jevin Sweval, Paul
-Swirhun, Shinya T-Y, Thierry Tambe, Jesse Taube, Drew Taussig, Christopher
+Swirhun, Krzysztof Sychla, Shinya T-Y, Yutetsu Takatsukasa, Thierry Tambe,
-Taylor, Greg Taylor, Jose Tejada, Sören Tempel, Peter Tengstrand, Wesley
+Jesse Taube, Drew Taussig, Christopher Taylor, David Taylor, Greg Taylor,
+Michael Bedford Taylor, Jose Tejada, Sören Tempel, Peter Tengstrand, Wesley
 Terpstra, Rui Terra, Stefan Thiede, Justin Thiel, Gary Thomas, Ian
-Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar, Tudor Timi, Viktor
+Thompson, Kevin Thompson, Mike Thyer, Jerry Tianchen, Hans Tichelaar, Tudor
-Tomov, Steve Tong, Topa Topino, Àlex Torregrosa, Topa Tota, Michael
+Timi, Viktor Tomov, Steve Tong, Topa Topino, Àlex Torregrosa, Topa Tota,
-Tresidder, Lenny Truong, David Turner, Neil Turton, Hideto Ueno, Mike
+Michael Tresidder, Lenny Truong, David Turner, Neil Turton, Hideto Ueno,
-Urbach, Joel Vandergriendt, Srini Vemuri, Srinivasan Venkataramanan, Yuri
+Ethan Uppal, Mike Urbach, Joel Vandergriendt, Srini Vemuri, Srinivasan
-Victorovich, Ivan Vnučec, Bogdan Vukobratovic, Holger Waechtler, Philipp
+Venkataramanan, Yuri Victorovich, Ivan Vnučec, Andrew Voznytsa, Bogdan
-Wagner, Stefan Wallentowitz, Johannes Walter, CY Wang, Chuxuan Wang, Shawn
+Vukobratovic, Holger Waechtler, Justin Wagner, Philipp Wagner, Stefan
-Wang, Yilou Wang, Zhanglei Wang, Greg Waters, Thomas Watts, Eugene Weber,
+Wallentowitz, Johannes Walter, CY Wang, Chuxuan Wang, Shawn Wang, Yilou
-John Wehle, Tianrui Wei, David Welch, Thomas J Whatson, Martin Whitaker,
+Wang, Zhanglei Wang, Jakub Wasilewski, Paul Wasson, Greg Waters, Thomas
-Marco Widmer, Leon Wildman, Daniel S. Wilkerson, Daniel Wilkerson, Gerald
+Watts, Eugene Weber, John Wehle, Tianrui Wei, Yin Weijie, David Welch,
-Williams, Trevor Williams, Don Williamson, Jan Van Winkel, Jeff Winston,
+Thomas J Whatson, Martin Whitaker, Marco Widmer, Leon Wildman, Daniel S.
-Joshua Wise, Clifford Wolf, Johan Wouters, Paul Wright, Tobias Wölfel,
+Wilkerson, Daniel Wilkerson, Gerald Williams, Trevor Williams, Don
-Junyi Xi, Ding Xiaoliang, Liu Xiaoyi, Jinyan Xu, Mandy Xu, Pengcheng Xu,
+Williamson, Jan Van Winkel, Jeff Winston, Max Wipfli, Joshua Wise, Clifford
-Shanshan Xu, Yan Xu, Yinan Xu, SU YANG, Felix Yan, Jiaxun Yang, Luke Yang,
+Wolf, Johan Wouters, Paul Wright, Tobias Wölfel, Domenic Wüthrich, Junyi
-Amir Yazdanbakhsh, Chentai (Seven) Yuan, Florian Zaruba, Mat Zeno, Keyi
+Xi, Ding Xiaoliang, Liu Xiaoyi, Jie Xu, Jinyan Xu, Mandy Xu, Pengcheng Xu,
-Zhang, Xi Zhang, Huanghuang Zhou, Yike Zhou, Jiamin Zhu, Ryan Ziegler.
+Shanshan Xu, Yan Xu, Yinan Xu, Felix Yan, Zhen Yan, Jiaxun Yang, Luke Yang,
+Su Yang, Amir Yazdanbakhsh, Law Heng Yi, Ibrahim Burak Yorulmaz, Chentai
+(Seven) Yuan, Florian Zaruba, Igor Zaworski, Mat Zeno, Keyi Zhang, Xi
+Zhang, Alex Zhou, Huanghuang Zhou, Yike Zhou, Jiamin Zhu, Ryan Ziegler, Lan
+Zongwei.
 
 Thanks to them, and all those we've missed mentioning above, and to those
 whom have wished to remain anonymous.
@@ -177,21 +203,21 @@ Historical Origins
 ==================
 
 Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group at
-Digital Equipment Corporation.  The Verilog code that was converted to C
+Digital Equipment Corporation. The Verilog code that was converted to C was
-was then merged with a C-based CPU model of the Alpha processor and
+then merged with a C-based CPU model of the Alpha processor and simulated
-simulated in a C-based environment called CCLI.
+in a C-based environment called CCLI.
 
 In 1995 Verilator started being used for Multimedia and Network Processor
-development inside Digital.  Duane Galbi took over the active development
+development inside Digital. Duane Galbi took over the active development of
-of Verilator, and added several performance enhancements, and CCLI was
+Verilator, and added several performance enhancements, and CCLI was still
-still being used as the shell.
+being used as the shell.
 
 In 1998, through the efforts of existing DECies, mainly Duane Galbi,
 Digital graciously agreed to release the source code. (Subject to the code
 not being resold, which is compatible with the GNU Public License.)
 
-In 2001, Wilson Snyder took the kit, added a SystemC mode, and called
+In 2001, Wilson Snyder took the kit, added a SystemC mode, and called it
-it Verilator2.  This was the first packaged public release.
+Verilator2. This was the first packaged public release.
 
 In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from
 scratch in C++. This added many optimizations, yielding about a 2-5x

docs/guide/copyright.rst

@@ -1,14 +1,13 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *********
 Copyright
 *********
 
-The latest version of Verilator is available from `https://verilator.org
+The latest version of Verilator is available from https://verilator.org.
-<https://verilator.org>`_.
 
-Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+Copyright 2003-2026 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.

docs/guide/deprecations.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Deprecations
@@ -13,16 +13,17 @@ C++14 compiler support
 
    Verilator will require C++20 or newer compilers for both compiling
    Verilator and compiling all Verilated models no sooner than May 2025.
-  (Likely to be removed shortly after GitHub removes Ubuntu 20.04
+   (Although this date has expired, this change is currently on hold until
-  continuous-integration action runners, which are used to test the older
+   the Ubuntu LTS versions of GCC and clang use C++20 by default, estimated
-  C++ standard).
+   May 2028.)
 
 XML output
-  Verilator currently supports XML parser output (enabled with `--xml-only`).
+   Verilator currently supports XML parser output (enabled with
-  Support for `--xml-*` options will be deprecated no sooner than January 2026.
+   `--xml-only`). Support for `--xml-*` options will be deprecated no
+   sooner than January 2026.
 
---make cmake
+`--make cmake`
-  The `--make cmake` options is deprecated and will be removed no sooner than
+   The `--make cmake` options is deprecated and will be removed no sooner
-  January 2026. Use `--make json` instead. Note that the CMake integration
+   than January 2026. Use `--make json` instead. Note that the CMake
-  shipping with Verilator (verilator-config.mk) already uses `--make json` so
+   integration shipping with Verilator (verilator-config.mk) already uses
-  no changes are necessary if using that.
+   `--make json` so no changes are necessary if using that.

docs/guide/environment.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Environment
@@ -10,8 +10,8 @@ associated programs.
 .. option:: LD_LIBRARY_PATH
 
    A generic Linux/OS variable specifying what directories have shared
-   object (.so) files.  This path should include SystemC and other
+   object (.so) files. This path should include SystemC and other shared
-   shared objects needed at simulation runtime.
+   objects needed at simulation runtime.
 
 .. option:: MAKE
 
@@ -29,28 +29,28 @@ associated programs.
 .. option:: OBJCACHE
 
    Optionally specifies a caching or distribution program to place in front
-   of all runs of the C++ compiler.  For example, "ccache" or "sccache".  If using
+   of all runs of the C++ compiler. For example, "ccache" or "sccache". If
-   :command:`distcc` or :command:`icecc`/:command:`icecream`, they would
+   using :command:`distcc` or :command:`icecc`/:command:`icecream`, they
-   generally be run under :command:`ccache`; see the documentation for
+   would generally be run under :command:`ccache`; see the documentation
-   those programs.  If OBJCACHE is not set, and at configure time ccache
+   for those programs. If OBJCACHE is not set, and at configure time ccache
    was present, ccache will be used as a default.
 
 .. option:: SYSTEMC
 
    Deprecated. Used only if :option:`SYSTEMC_INCLUDE` or
    :option:`SYSTEMC_LIBDIR` is not set. If set, specifies the directory
-   containing the SystemC distribution.  If not specified, it will come
+   containing the SystemC distribution. If not specified, it will come from
-   from a default optionally specified at configure time (before Verilator
+   a default optionally specified at configure time (before Verilator was
-   was compiled).
+   compiled).
 
 .. option:: SYSTEMC_ARCH
 
-   Deprecated.  Used only if :option:`SYSTEMC_LIBDIR` is not set.
+   Deprecated. Used only if :option:`SYSTEMC_LIBDIR` is not set. Specifies
-   Specifies the architecture name used by the SystemC kit.  This is the
+   the architecture name used by the SystemC kit. This is the part after
-   part after the dash in the "lib-{...}" directory name created by a
+   the dash in the "lib-{...}" directory name created by a :command:`make`
-   :command:`make` in the SystemC distribution.  If not set, Verilator will
+   in the SystemC distribution. If not set, Verilator will try to intuit
-   try to intuit the proper setting, or use the default optionally
+   the proper setting, or use the default optionally specified at configure
-   specified at configure time (before Verilator was compiled).
+   time (before Verilator was compiled).
 
 .. option:: SYSTEMC_CXX_FLAGS
 
@@ -121,13 +121,15 @@ associated programs.
 .. option:: VERILATOR_SOLVER
 
    If set, the command to run as a constrained randomization backend, such
-   as :command:`cvc4 --lang=smt2 --incremental`.  If not specified, it will use
+   as :command:`cvc4 --lang=smt2 --incremental`. If not specified, it will
-   the one supplied or found during configure, or :command:`z3 --in` if empty.
+   use the one supplied or found during configure, or :command:`z3 --in` if
+   empty.
 
 .. option:: VERILATOR_VALGRIND
 
-   If set, the command to run when using the :vlopt:`--valgrind` option, such as
+   If set, the command to run when using the :vlopt:`--valgrind` option,
-   "valgrind --tool=callgrind".  If not specified, it will use "valgrind".
+   such as "valgrind --tool=callgrind". If not specified, it will use
+   "valgrind".
 
 
 Make Variables

docs/guide/example_binary.rst

@@ -1,14 +1,14 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Example Create-Binary Execution:
+.. _example create-binary execution:
 
 Example Create-Binary Execution
 ===============================
 
-We'll compile this SystemVerilog example into a Verilated simulation binary.  For
+We'll compile this SystemVerilog example into a Verilated simulation
-an example that discusses the next level of detail see :ref:`Example C++
+binary. For an example that discusses the next level of detail see
-Execution`.
+:ref:`Example C++ Execution`.
 
 .. include:: example_common_install.rst
 
@@ -39,8 +39,7 @@ Breaking this command down:
 #. :vlopt:`-j` `0` to Verilate using use as many CPU threads as the machine
    has.
 
-#. :vlopt:`-Wall` so Verilator has stronger lint warnings
+#. :vlopt:`-Wall` so Verilator has stronger lint warnings enabled.
-   enabled.
 
 #. An finally, :command:`our.v`, which is our SystemVerilog design file.
 

docs/guide/example_cc.rst

@@ -1,7 +1,7 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Example C++ Execution:
+.. _example c++ execution:
 
 Example C++ Execution
 =====================
@@ -60,8 +60,7 @@ Breaking this command down:
 #. :vlopt:`-j 0 <-j>` to Verilate using use as many CPU threads as the
    machine has.
 
-#. :vlopt:`-Wall` so Verilator has stronger lint warnings
+#. :vlopt:`-Wall` so Verilator has stronger lint warnings enabled.
-   enabled.
 
 #. And finally, :command:`our.v` which is our SystemVerilog design file.
 

docs/guide/example_common_install.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 First you need Verilator installed, see :ref:`Installation`. In brief, if

docs/guide/example_dist.rst

@@ -1,41 +1,51 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Examples in the Distribution:
+.. _examples in the distribution:
 
 Examples in the Distribution
 ============================
 
-See the ``examples/`` directory that is part of the distribution, and
+See the ``examples/`` directory that is part of the distribution, and is
-is installed (in an OS-specific place, often in e.g.
+installed (in an OS-specific place, often in e.g.
 ``/usr/local/share/verilator/examples``). These examples include:
 
 examples/make_hello_binary
    Example GNU-make simple Verilog->binary conversion
+
 examples/make_hello_c
    Example GNU-make simple Verilog->C++ conversion
+
 examples/make_hello_sc
    Example GNU-make simple Verilog->SystemC conversion
+
 examples/make_tracing_c
    Example GNU-make Verilog->C++ with tracing
+
 examples/make_tracing_sc
    Example GNU-make Verilog->SystemC with tracing
+
 examples/make_protect_lib
    Example using --protect-lib
+
 examples/cmake_hello_c
    Example building make_hello_c with CMake
+
 examples/cmake_hello_sc
    Example building make_hello_sc with CMake
+
 examples/cmake_tracing_c
    Example building make_tracing_c with CMake
+
 examples/cmake_tracing_sc
    Example building make_tracing_sc with CMake
+
 examples/cmake_protect_lib
    Example building make_protect_lib with CMake
 
 To run an example copy the example to a new directory and run it.
 
-::
+.. code-block:: bash
 
    cp -rp {path_to}/examples/make_hello_c make_hello_c
    cd make_hello_c

docs/guide/example_sc.rst

@@ -1,7 +1,7 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Example SystemC Execution:
+.. _example systemc execution:
 
 Example SystemC Execution
 =========================

docs/guide/examples.rst

@@ -1,7 +1,7 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Examples:
+.. _examples:
 
 ========
 Examples

docs/guide/exe_sim.rst

@@ -1,14 +1,14 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Simulation Runtime Arguments:
+.. _simulation runtime arguments:
 
 Simulation Runtime Arguments
 ============================
 
 The following are the arguments that may be passed to a Verilated
 executable, provided that executable calls
-:code:`VerilatedContext*->commandArgs(argc, argv)`.
+``VerilatedContext*->commandArgs(argc, argv)``.
 
 All simulation runtime arguments begin with "+verilator", so that the
 user's executable may skip over all "+verilator" arguments when parsing its
@@ -18,6 +18,7 @@ Summary:
 
    .. include:: ../_build/gen/args_verilated.rst
 
+Options:
 
 .. option:: +verilator+coverage+file+<filename>
 
@@ -50,7 +51,7 @@ Summary:
 .. option:: +verilator+noassert
 
    Disable assert checking per runtime argument. This is the same as
-   calling :code:`VerilatedContext*->assertOn(false)` in the model.
+   calling ``VerilatedContext*->assertOn(false)`` in the model.
 
 .. option:: +verilator+prof+exec+file+<filename>
 
@@ -72,9 +73,9 @@ Summary:
    When a model was Verilated using :vlopt:`--prof-exec`, after $time
    reaches :vlopt:`+verilator+prof+exec+start+\<value\>`, Verilator will
    warm up the profiling for this number of eval() calls, then will capture
-   the profiling of this number of eval() calls.  Defaults to 2, which
+   the profiling of this number of eval() calls. Defaults to 2, which makes
-   makes sense for a single-clock-domain module where it's typical to want
+   sense for a single-clock-domain module where it's typical to want to
-   to capture one posedge eval() and one negedge eval().
+   capture one posedge eval() and one negedge eval().
 
 .. option:: +verilator+prof+threads+file+<filename>
 
@@ -104,10 +105,10 @@ Summary:
 
 .. option:: +verilator+rand+reset+<value>
 
-   When a model was Verilated using
+   When a model was Verilated using :vlopt:`--x-initial unique
-   :vlopt:`--x-initial unique <--x-initial>`, sets the simulation runtime
+   <--x-initial>`, sets the simulation runtime initialization technique. 0
-   initialization technique.  0 = Reset to zeros. 1 = Reset to all-ones.  2
+   = Reset to zeros. 1 = Reset to all-ones. 2 = Randomize. See
-   = Randomize.  See :ref:`Unknown States`.
+   :ref:`Unknown States`.
 
 .. option:: +verilator+seed+<value>
 

docs/guide/exe_verilator_coverage.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_coverage
@@ -24,13 +24,14 @@ statement to the appropriate statement block, or see
 :option:`/*verilator&32;coverage_off*/`. This will remove the coverage
 points after the model is re-Verilated.
 
-For an overview of the use of verilator_coverage, see :ref:`Coverage Analysis`.
+For an overview of the use of verilator_coverage, see :ref:`Coverage
+Analysis`.
 
 
 verilator_coverage Example Usage
 --------------------------------
 
-..
+.. code-block:: bash
 
    verilator_coverage --help
    verilator_coverage --version
@@ -59,8 +60,8 @@ verilator_coverage Arguments
    coverage data should be written.
 
    Points are children of each line coverage- branches, expressions or
-   toggle points.  When point counts are aggregated into a line, the
+   toggle points. When point counts are aggregated into a line, the minimum
-   minimum and maximum counts are used to determine the status of the line
+   and maximum counts are used to determine the status of the line
    (complete, partial, failing) The count is equal to the maximum of the
    points.
 
@@ -73,7 +74,8 @@ verilator_coverage Arguments
    * "%" indicates that all points on the line are below the coverage min.
    * "~" indicates that some points on the line are above the coverage min and some are below.
    * "+" coverage point was at or above the min. Only used with :option:`--annotate-points`.
-   * "-" coverage point was below the min.  Only used with :option:`--annotate-points`.
+   * "-" coverage point was below the min. Only used with
+     :option:`--annotate-points`.
 
    .. code-block::
 
@@ -92,8 +94,8 @@ verilator_coverage Arguments
 
 .. option:: --annotate-all
 
-   Specifies all files should be shown.  By default, only those source
+   Specifies all files should be shown. By default, only those source files
-   files with low coverage are written to the output directory.
+   with low coverage are written to the output directory.
 
    This option should be used together with :option:`--annotate`.
 
@@ -111,8 +113,8 @@ verilator_coverage Arguments
 
 .. option:: --annotate-points
 
-   Specifies all coverage points should be shown after each line of text.  By
+   Specifies all coverage points should be shown after each line of text.
-   default, only source lines are shown.
+   By default, only source lines are shown.
 
    .. code-block::
 

docs/guide/exe_verilator_gantt.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_gantt
@@ -31,17 +31,17 @@ In waveforms, there are the following signals. In GTKWave, use "decimal"
 data format to remove the leading zeros and make the traces easier to read.
 
 trace/section
-  Shows the name of the current top of the execution section stack.
+   Shows the name of the current top of the execution section stack. Set
-  Set GTKWave data format to "ASCII".
+   GTKWave data format to "ASCII".
 
 trace/depth
-  Shows the depth of the execution section stack.
+   Shows the depth of the execution section stack. Set GTKWave data format
-  Set GTKWave data format to "Analog".
+   to "Analog".
 
 measured_parallelism
-  The number of mtasks active at this time, for best performance, this will
+   The number of mtasks active at this time, for best performance, this
-  match the thread count. In GTKWave, use a data format of "analog step" to
+   will match the thread count. In GTKWave, use a data format of "analog
-  view this signal.
+   step" to view this signal.
 
 predicted_parallelism
    The number of mtasks Verilator predicted would be active at this time,
@@ -52,8 +52,8 @@ cpu#_thread
    For the given CPU number, the thread number measured to be executing.
 
 cpu#_waiting
-  For the given CPU number, aggregated waiting time for mtask dependencies.
+   For the given CPU number, aggregated waiting time for mtask
-  Visualized as `X` values.
+   dependencies. Visualized as `X` values.
 
 mtask#_cpu
    For the given mtask id, the CPU it was measured to execute on.
@@ -69,7 +69,7 @@ predicted_thread#_mtask
 verilator_gantt Example Usage
 -----------------------------
 
-..
+.. code-block:: bash
 
    verilator_gantt --help
    verilator_gantt --version

docs/guide/exe_verilator_profcfunc.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_profcfunc
@@ -10,15 +10,15 @@ the functions are then transformed, assuming the user used Verilator's
 etc., in each Verilog block.
 
 Due to rounding errors in gprof reports, the input report's percentages may
-not total 100%.  In the verilator_profcfunc report this will get
+not total 100%. In the verilator_profcfunc report this will get reported as
-reported as a rounding error.
+a rounding error.
 
 For an overview of the use of verilator_profcfunc, see :ref:`Profiling`.
 
 verilator_profcfunc Example Usage
 ---------------------------------
 
-..
+.. code-block:: bash
 
    verilator_profcfunc --help
    verilator_profcfunc --version

docs/guide/executables.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *********************************

docs/guide/extensions.rst

@@ -1,9 +1,9 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-=====================
+===================
- Language Extensions
+Language Extensions
-=====================
+===================
 
 The following additional constructs are the extensions Verilator supports
 on top of standard Verilog code. Using these features outside of comments
@@ -73,10 +73,9 @@ or "`ifdef`"'s may break other tools.
 
    Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
-   verbatim into the output .h file's header.  Must be placed as a module
+   verbatim into the output .h file's header. Must be placed as a module or
-   or class item, e.g., directly inside a module/endmodule or
+   class item, e.g., directly inside a module/endmodule or class/endclass
-   class/endclass pair. Despite the name of this macro, this also works in
+   pair. Despite the name of this macro, this also works in pure C++ code.
-   pure C++ code.
 
 .. option:: `systemc_header_post
 
@@ -142,16 +141,16 @@ or "`ifdef`"'s may break other tools.
 .. option:: `VERILATOR_TIMING
 
    The VERILATOR_TIMING define is set when :vlopt:`--timing` is used to
-   allow an "\`ifdef" of code dependent on this feature.  Note that this define
+   allow an "\`ifdef" of code dependent on this feature. Note that this
-   is not affected by the :option:`timing_off` control file option
+   define is not affected by the :option:`timing_off` control file option
    nor timing metacomments.
 
 .. option:: `verilog
 
-   Switch back to processing Verilog code after a
+   Switch back to processing Verilog code after a :option:`\`systemc_...
-   :option:`\`systemc_... <\`systemc_header>` mode switch.  The Verilog
+   <\`systemc_header>` mode switch. The Verilog code returns to the last
-   code returns to the last language mode specified with
+   language mode specified with "\`begin_keywords", or SystemVerilog if
-   "\`begin_keywords", or SystemVerilog if none was specified.
+   none was specified.
 
 
    .. t_dist_docs_style restart_sort
@@ -171,28 +170,27 @@ or "`ifdef`"'s may break other tools.
    via an explicit 'this->' pointer dereference.
 
    Expression arguments will have the code to evaluate the expression
-   inserted.  Thus to call a C++ function, :code:`$c("func(",a,")")` will
+   inserted. Thus to call a C++ function, ``$c("func(",a,")")`` will result
-   result in :code:`func(a)` in the output C++ code.  For input arguments,
+   in ``func(a)`` in the output C++ code. For input arguments, rather than
-   rather than hard-coding variable names in the string
+   hard-coding variable names in the string ``$c("func(a)")``, instead pass
-   :code:`$c("func(a)")`, instead pass the variable as an expression
+   the variable as an expression :``$c("func(",a,")")``. This will allow
-   ::code:`$c("func(",a,")")`.  This will allow the call to work inside
+   the call to work inside Verilog functions where the variable is
-   Verilog functions where the variable is flattened out and enable other
+   flattened out and enable other optimizations.
-   optimizations.
 
    Verilator does not use any text inside the quotes for
-   ordering/scheduling.  If you need the $c to be called at a specific
+   ordering/scheduling. If you need the $c to be called at a specific time,
-   time, e.g., when a variable changes, then the $c must be under an
+   e.g., when a variable changes, then the $c must be under an appropriate
-   appropriate sensitivity statement, e.g.,
+   sensitivity statement, e.g., ``always @(posedge clk) $c("func()")`` to
-   :code:`always @(posedge clk) $c("func()")` to call it on every edge, or,
+   call it on every edge, or, e.g., ``always @* c("func(",a,")")`` to call
-   e.g., :code:`always @* c("func(",a,")")` to call it when :code:`a`
+   it when ``a`` changes (the latter working because ``a`` is outside the
-   changes (the latter working because :code:`a` is outside the quotes).
+   quotes).
 
    If you will be reading or writing any Verilog variables inside the C++
    functions, the Verilog signals must be declared with
    :option:`/*verilator&32;public*/` metacomments.
 
-   You may also append a number to $c, which specifies the bit width of
+   You may also append a number to $c, which specifies the bit width of the
-   the output, e.g., :code:`signal_32_bits = $c32("...");`.  This allows for
+   output, e.g., ``signal_32_bits = $c32("...");``. This allows for
    compatibility with other simulators, which require a differently named
    PLI function name for each different output width.
 
@@ -205,8 +203,8 @@ or "`ifdef`"'s may break other tools.
 
    Format arguments may use C fprintf sizes after the % escape. Per the
    Verilog standard, %x prints a number with the natural width, and %0x
-   prints a number with minimum width.  Verilator extends this so %5x
+   prints a number with minimum width. Verilator extends this so %5x prints
-   prints 5 digits per the C standard. This extension was standardized into
+   5 digits per the C standard. This extension was standardized into
    1800-2009.
 
 .. option:: $stacktrace
@@ -216,8 +214,8 @@ or "`ifdef`"'s may break other tools.
    may give less meaningful results if the model is not compiled with debug
    symbols. Also, the data represents the C++ stack; the SystemVerilog
    functions/tasks involved may be renamed and/or inlined before becoming
-   the C++ functions that may be visible in the stack trace.  This
+   the C++ functions that may be visible in the stack trace. This extension
-   extension was standardized in IEEE 1800-2023.
+   was standardized in IEEE 1800-2023.
 
 .. option:: $timeprecision
 
@@ -226,8 +224,8 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: $timeunit
 
-   Returns the timeunit of the current module as an integer.  This
+   Returns the timeunit of the current module as an integer. This extension
-   extension is experimental and may be removed without deprecation.
+   is experimental and may be removed without deprecation.
 
 .. option:: /*verilator&32;clock_enable*/
 
@@ -287,6 +285,15 @@ or "`ifdef`"'s may break other tools.
    (if appropriate :vlopt:`--coverage` flags are passed) after being
    disabled earlier with :option:`/*verilator&32;coverage_off*/`.
 
+.. option:: /*verilator&32;fargs <arguments>*/
+
+   For Verilator developers only. When a source file containing these `fargs`
+   metacomments is passed to Verilator on the command line via the :vlopt:`-f`
+   or :vlopt:`-F` option, the provided arguments will be added as if specified
+   on the command line. The source file is not preprocessed before parsing for
+   arguments, and all `fargs` comments will take effect, even if placed
+   undef an inactive `\`ifdef`.
+
 .. option:: /*verilator&32;forceable*/
 
    Specifies that the signal (net or variable) should be made forceable from
@@ -307,9 +314,9 @@ or "`ifdef`"'s may break other tools.
 .. option:: /*verilator&32;hier_block*/
 
    Specifies that the module is a unit of hierarchical Verilation. This
-   metacomment must be between :code:`module module_name(...);` and
+   metacomment must be between ``module module_name(...);`` and
-   :code:`endmodule`.  The module will not be inlined nor uniquified for
+   ``endmodule``. The module will not be inlined nor uniquified for each
-   each instance in hierarchical Verilation.  Note that the metacomment is
+   instance in hierarchical Verilation. Note that the metacomment is
    ignored unless the :vlopt:`--hierarchical` option is specified.
 
    See :ref:`Hierarchical Verilation`.
@@ -319,8 +326,8 @@ or "`ifdef`"'s may break other tools.
    Specifies the module the comment appears in may be inlined into any
    modules that use this module. This is useful to speed up simulation
    runtime. Note if using :vlopt:`--public` that signals under inlined
-   submodules will be named :code:`{submodule}__DOT__{subsignal}` as C++
+   submodules will be named ``{submodule}__DOT__{subsignal}`` as C++ does
-   does not allow "." in signal names.
+   not allow "." in signal names.
 
    Same as :option:`inline` control file option.
 
@@ -374,8 +381,8 @@ or "`ifdef`"'s may break other tools.
 
    If a one-line slash-slash-format comment is used, then the metacomment
    ends at the newline or at an earlier next slash-slash. This allow
-   commenting the reason for the disable, e.g. :code:`// verilator lint_off
+   commenting the reason for the disable, e.g. ``// verilator lint_off
-   MSG // Because...`.
+   MSG // Because...``.
 
 .. option:: /*verilator&32;lint_on <msgs>*/
 
@@ -384,15 +391,15 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: /*verilator&32;lint_restore*/
 
-   After a :code:`/*verilator&32;lint_save*/`, pop the stack containing lint
+   After a ``/*verilator&32;lint_save*/``, pop the stack containing lint
    message state. Often this is useful at the bottom of include files.
 
 .. option:: /*verilator&32;lint_save*/
 
-   Push the current state of what lint messages are turned on or off
+   Push the current state of what lint messages are turned on or off to a
-   to a stack.  Later meta-comments may then lint_on or lint_off specific
+   stack. Later meta-comments may then lint_on or lint_off specific
    messages, then return to the earlier message state by using
-   :code:`/*verilator&32;lint_restore*/`.  For example:
+   ``/*verilator&32;lint_restore*/``. For example:
 
    .. code-block:: sv
 
@@ -416,9 +423,8 @@ or "`ifdef`"'s may break other tools.
    Used in a function or task variable definition section to specify the
    function or task should not be inlined into where it is used. This may
    reduce the size of the final executable when a task is used a very large
-   number of times.  For this flag to work, the task and tasks below it
+   number of times. For this flag to work, the task and tasks below it must
-   must be pure; they cannot reference any variables outside the task
+   be pure; they cannot reference any variables outside the task itself.
-   itself.
 
    Same as :option:`no_inline` control file option.
 
@@ -471,7 +477,7 @@ or "`ifdef`"'s may break other tools.
    Used after an input, output, register, or wire declaration to indicate
    the signal should be declared so that C code may read or write the value
    of the signal. This will also declare this module public; otherwise, use
-   :code:`/*verilator&32;public_flat*/`.
+   ``/*verilator&32;public_flat*/``.
 
    Instead of using public variables, consider making a DPI or public
    function that accesses the variable. This is nicer as it provides an
@@ -506,8 +512,8 @@ or "`ifdef`"'s may break other tools.
 
    Used after an input, output, register, or wire declaration to indicate
    the signal should be declared so that C code may read or write the value
-   of the signal.  This will not declare this module public, which means
+   of the signal. This will not declare this module public, which means the
-   the name of the signal or path to it may change based upon the module
+   name of the signal or path to it may change based upon the module
    inlining which takes place.
 
    Same as :option:`public_flat` control file option.
@@ -537,8 +543,8 @@ or "`ifdef`"'s may break other tools.
    Used after a module statement to indicate the module should not be
    inlined (unless specifically requested) so that C code may access the
    module. Verilator automatically sets this attribute when the module
-   contains public signals or \`systemc_ directives.  Use of this is
+   contains public signals or \`systemc_ directives. Use of this is implied
-   implied when using the :vlopt:`--public` option.
+   when using the :vlopt:`--public` option.
 
    Same as :option:`public` control file option.
 
@@ -546,14 +552,23 @@ or "`ifdef`"'s may break other tools.
 
    Terminates the previous `/*verilator public*_on*/` directive; see above.
 
+.. option:: /*verilator&32;sc_biguint*/
+
+   Used after a port declaration. It sets the port to be of
+   ``sc_biguint<{width}>`` type, for signals of any width. This may be
+   useful if the port width is parameterized and the instantiating C++ code
+   always wants to have a sc_biguint accept any width. In general, you
+   should avoid using this attribute when unnecessary, as the performance
+   decreases significantly with increasing usage of sc_biguint.
+
 .. option:: /*verilator&32;sc_bv*/
 
    Used after a port declaration. It sets the port to be of
-   :code:`sc_bv<{width}>` type, instead of bool, uint32_t, or uint64_t.
+   ``sc_bv<{width}>`` type, instead of bool, uint32_t, or uint64_t. This
-   This may be useful if the port width is parameterized and the
+   may be useful if the port width is parameterized and the instantiating
-   instantiating C++ code always wants to have a sc_bv accept any width.
+   C++ code always wants to have a sc_bv accept any width. In general, you
-   In general, you should avoid using this attribute when unnecessary, as
+   should avoid using this attribute when unnecessary, as the performance
-   the performance decreases significantly with increasing usage of sc_bv.
+   decreases significantly with increasing usage of sc_bv.
 
    Same as :option:`sc_bv` control file option.
 
@@ -561,9 +576,9 @@ or "`ifdef`"'s may break other tools.
 
    Deprecated and ignored. Previously used after an input declaration to
    indicate the signal should be declared in SystemC as a sc_clock instead
-   of a bool.  This was needed in SystemC 1.1 and 1.2 only; versions 2.0
+   of a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0 and
-   and later do not require clock pins to be sc_clocks, and this is no
+   later do not require clock pins to be sc_clocks, and this is no longer
-   longer needed and is ignored.
+   needed and is ignored.
 
 .. option:: /*verilator&32;sformat*/
 
@@ -619,7 +634,6 @@ or "`ifdef`"'s may break other tools.
       assign tmp[1] = tmp[1] + b;
       assign bar    = tmp[1] + c;
 
-
    Same as :option:`split_var` control file option.
 
 .. option:: /*verilator&32;tag <text...>*/
@@ -632,8 +646,8 @@ or "`ifdef`"'s may break other tools.
 
    Ignore all timing constructs after this metacomment. All timing controls
    behave as if they were not there (the same way as with
-   :option:`--no-timing`), and :code:`fork`/:code:`join*` blocks are
+   :option:`--no-timing`), and ``fork``/``join*`` blocks are
-   converted into :code:`begin`/:code:`end` blocks.
+   converted into ``begin``/``end`` blocks.
 
    Same as :option:`timing_off` control file option.
 
@@ -681,5 +695,5 @@ or "`ifdef`"'s may break other tools.
 
    Rarely needed. Used in a statement position to indicate the immediately
    following loop at the same statement level should always be fully
-   unrolled by Verilator, ignoring :vlopt:`--unroll-count`.  This is
+   unrolled by Verilator, ignoring :vlopt:`--unroll-count`. This is similar
-   similar to clang's ``#pragma clang loop unroll(full)``.
+   to clang's ``#pragma clang loop unroll(full)``.

docs/guide/faq.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ******************************
@@ -13,9 +13,9 @@ Questions
 Can I contribute?
 """""""""""""""""
 
-Please contribute!  Just submit a pull request, or raise an issue to
+Please contribute! Just submit a pull request, or raise an issue to discuss
-discuss if you are looking for something to help on.  For more information
+if you are looking for something to help on. For more information see our
-see our contributor agreement.
+contributor agreement.
 
 
 How widely is Verilator used?
@@ -25,10 +25,10 @@ Verilator is used by many of the largest silicon design companies, large
 organizations such as CERN, and even by college student projects.
 
 Verilator is one of the "big 4" simulators, meaning one of the four leading
-SystemVerilog simulators available, namely the closed-source products Synopsys
+SystemVerilog simulators available, namely the closed-source products
-VCS (tm), Mentor Questa/ModelSim (tm), Cadence
+Synopsys VCS (tm), Mentor Questa/ModelSim (tm), Cadence
-Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator.
+Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator. The
-The three closed-source offerings are often collectively called the "big 3"
+three closed-source offerings are often collectively called the "big 3"
 simulators.
 
 
@@ -65,14 +65,15 @@ optimizations, which are where most of the gains come from.
 
 You should not be scared by non-compliance. Your synthesis tool isn't
 compliant with the whole standard to start with, so your simulator need not
-be either.  Verilator is closer to the synthesis interpretation, which is
+be either. Verilator is closer to the synthesis interpretation, which is a
-a good thing for getting working silicon.
+good thing for getting working silicon.
 
 
 Will Verilator output remain under my own license/copyright?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-Your SystemVerilog, VPI/DPI, or main() C++ code remains under your own license.
+Your SystemVerilog, VPI/DPI, or main() C++ code remains under your own
+license.
 
 It's just like how using GCC on your programs does not change the copyright
 of your program; this is why Verilator uses the "GNU **Lesser** Public
@@ -101,9 +102,9 @@ license also allows you to modify Verilator for internal use without
 distributing the modified version. But please contribute back to the
 community!
 
-Under both licenses, you can offer a commercial product based on
+Under both licenses, you can offer a commercial product based on Verilator
-Verilator directly or embedded within.  However, under both licenses,
+directly or embedded within. However, under both licenses, any changes you
-any changes you make to Verilator for such a product must be open-sourced.
+make to Verilator for such a product must be open-sourced.
 
 As is standard with Open Source, contributions back to Verilator will be
 placed under the Verilator copyright and LGPL/Artistic license. Small test
@@ -114,13 +115,13 @@ and large tests under the LGPL/Artistic, unless requested otherwise.
 Why is running Verilator (to create a model) so slow?
 """""""""""""""""""""""""""""""""""""""""""""""""""""
 
-Verilator may require more memory than the resulting simulation,
+Verilator may require more memory than the resulting simulation, as
-as Verilator internally creates all of the state of the resulting
+Verilator internally creates all of the state of the resulting generated
-generated simulator to optimize it.  If it takes more than a few
+simulator to optimize it. If it takes more than a few minutes or so (and
-minutes or so (and you're not using :vlopt:`--debug` since debug mode is
+you're not using :vlopt:`--debug` since debug mode is disk bound), see if
-disk bound), see if your machine is paging; most likely, you need to run it
+your machine is paging; most likely, you need to run it on a machine with
-on a machine with more memory. Very large designs are known to have topped
+more memory. Very large designs are known to have topped 64 GB resident set
-64 GB resident set size.  Alternatively, see :ref:`Hierarchical Verilation`.
+size. Alternatively, see :ref:`Hierarchical Verilation`.
 
 
 How do I generate waveforms (traces) in C++?
@@ -128,10 +129,10 @@ How do I generate waveforms (traces) in C++?
 
 See also the next question for tracing in SystemC mode.
 
-A. Pass the :vlopt:`--trace-vcd` option to Verilator.  Then you may use ``$dumpfile`` and
+A. Pass the :vlopt:`--trace-vcd` option to Verilator. Then you may use
-   ``$dumpvars`` to enable traces, the same as with any Verilog simulator,
+   ``$dumpfile`` and ``$dumpvars`` to enable traces, the same as with any
-   although Verilator ignores the arguments to ``$dumpvars``. See
+   Verilog simulator, although Verilator ignores the arguments to
-   ``examples/make_tracing_c`` in the distribution.
+   ``$dumpvars``. See ``examples/make_tracing_c`` in the distribution.
 
    If writing the top-level C code, call ``Verilated::traceEverOn(true)``;
    this is done for you if using :vlopt:`--binary`.
@@ -166,23 +167,22 @@ B. Or, for finer-grained control, or C++ files with multiple Verilated
 
 You also need to compile :file:`verilated_vcd_c.cpp` and add it to your
 link, preferably by adding the dependencies in your Makefile's
-:code:`$(VK_GLOBAL_OBJS)` link rule.  This is done for you if you are using
+``$(VK_GLOBAL_OBJS)`` link rule. This is done for you if you are using the
-the Verilator :vlopt:`--binary` or :vlopt:`--exe` option.
+Verilator :vlopt:`--binary` or :vlopt:`--exe` option.
 
-you can call :code:`trace_object->trace()` on multiple Verilated objects
+you can call ``trace_object->trace()`` on multiple Verilated objects with
-with the same trace file if you want all data to land in the same output
+the same trace file if you want all data to land in the same output file.
-file.
 
 
 How do I generate waveforms (traces) in SystemC?
 """"""""""""""""""""""""""""""""""""""""""""""""
 
 A. Pass the :vlopt:`--trace-vcd` option to Verilator, and in your top-level
-   :code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`.  Then you
+   ``sc_main()``, call ``Verilated::traceEverOn(true)``. Then you may use
-   may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, as
+   ``$dumpfile`` and code:`$dumpvars` to enable traces, as with any Verilog
-   with any Verilog simulator; see the non-SystemC example in
+   simulator; see the non-SystemC example in
    :file:`examples/make_tracing_c`. This will trace only the module
-   containing the :code:`$dumpvar`.
+   containing the ``$dumpvar``.
 
 B. Or, you may create a trace purely from SystemC, which may trace all
    Verilated designs in the SystemC model. Create a VerilatedVcdSc object
@@ -212,15 +212,13 @@ C. Alternatively, you may use the C++ trace mechanism described in the
           tfp->close();
       }
 
-
-
 You also need to compile :file:`verilated_vcd_sc.cpp` and
 :file:`verilated_vcd_c.cpp` and add them to your link, preferably by adding
-the dependencies in your Makefile's :code:`$(VK_GLOBAL_OBJS)` link rule.
+the dependencies in your Makefile's ``$(VK_GLOBAL_OBJS)`` link rule. This
-This is done for you if you are using the Verilator :vlopt:`--binary` or
+is done for you if you are using the Verilator :vlopt:`--binary` or
 :vlopt:`--exe` option.
 
-You can call :code:`->trace()` on multiple Verilated objects with the same
+You can call ``->trace()`` on multiple Verilated objects with the same
 trace file if you want all data to land in the same output file.
 
 
@@ -231,25 +229,23 @@ FST is a trace file format developed by GTKWave.  Verilator provides basic
 FST support. To dump traces in FST format, add the :vlopt:`--trace-fst`
 option to Verilator and either:
 
-Use :code:`$dumpfile & $dumpvars` in Verilog as described in the VCD
+Use ``$dumpfile & $dumpvars`` in Verilog as described in the VCD example
-example above,
+above,
 
 Or, in C++ change the include described in the VCD example above:
 
-  .. code-block:: C++
+.. code-block:: C++
 
    #include "verilated_fst_c.h"
    VerilatedFstC* tfp = new VerilatedFstC;
 
-
 Or, in SystemC, change the include described in the VCD example above:
 
-  .. code-block:: C++
+.. code-block:: C++
 
    #include "verilated_fst_sc.h"
    VerilatedFstC* tfp = new VerilatedFstSc;
 
-
 Currently, supporting FST and VCD in a single simulation is not supported,
 but such usage should be unlikely. You can however ifdef around the trace
 format in your C++ main loop, and select VCD or FST at compile time.
@@ -258,11 +254,11 @@ format in your C++ main loop, and select VCD or FST at compile time.
 How do I view waveforms (aka dumps or traces)?
 """"""""""""""""""""""""""""""""""""""""""""""
 
-Verilator creates standard VCD (Value Change Dump) and FST files.  VCD
+Verilator creates standard VCD (Value Change Dump) and FST files. VCD files
-files are viewable with the open-source
+are viewable with the open-source `GTKWave
-`GTKWave <https://gtkwave.sourceforge.net/>`_,
+<https://gtkwave.sourceforge.net/>`_, `Surfer
-`Surfer <https://surfer-project.org/>`_, Dinotrace (legacy), or any of the
+<https://surfer-project.org/>`_, Dinotrace (legacy), or any of the many
-many closed-source viewer offerings; FST is supported only by GTKWave and
+closed-source viewer offerings; FST is supported only by GTKWave and
 Surfer.
 
 
@@ -291,7 +287,7 @@ E. Write your trace files to a machine-local solid-state drive instead of a
 
 
 Where is the translate_off command? (How do I ignore a construct?)
-"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
 Translate on/off pragmas are generally a bad idea, as it's easy to have
 mismatched pairs, and you can't see what another tool sees by just
@@ -299,7 +295,7 @@ preprocessing the code.  Instead, use the preprocessor; Verilator defines
 the ``\`VERILATOR`` define for you, so just wrap the code in an ifndef
 region:
 
- .. code-block:: sv
+.. code-block:: sv
    :emphasize-lines: 1
 
    `ifndef VERILATOR
@@ -312,9 +308,9 @@ Most synthesis tools similarly define SYNTHESIS for you.
 Why do I get "unexpected 'do'" or "unexpected 'bit'" errors?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-The words \ ``do``\ , \ ``bit``\ , \ ``ref``\ , \ ``return``\ , and others
+The words ``do``, ``bit``, ``ref``, ``return``, and others are reserved
-are reserved keywords in SystemVerilog.  Older Verilog code might use these
+keywords in SystemVerilog. Older Verilog code might use these as
-as identifiers, and you should change your code to not use them to ensure it
+identifiers, and you should change your code to not use them to ensure it
 works with newer tools. Alternatively, surround them by the Verilog
 2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code.
 
@@ -325,7 +321,6 @@ works with newer tools.  Alternatively, surround them by the Verilog
       integer bit; initial bit = 1;
    `end_keywords
 
-
 If you want the whole design parsed as Verilog 2001, see the
 :vlopt:`--default-language` option.
 
@@ -333,8 +328,8 @@ If you want the whole design parsed as Verilog 2001, see the
 How do I prevent my assertions from firing during reset?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-Call :code:`Verilated::assertOn(false)` before you first call the model,
+Call ``Verilated::assertOn(false)`` before you first call the model, then
-then turn it back on after reset.  It defaults to true.  When false, all
+turn it back on after reset. It defaults to true. When false, all
 assertions are disabled.
 
 
@@ -343,22 +338,22 @@ Why do I get "undefined reference to sc_time_stamp()?
 
 In Verilator 4.200 and later, using the timeInc function is recommended
 instead. See the :ref:`Connecting to C++` examples. Some linkers (MSVC++)
-still require :code:`sc_time_stamp()` to be defined; either define this
+still require ``sc_time_stamp()`` to be defined; either define this with
-with :code:`double sc_time_stamp() { return 0; }` or compile the Verilated
+``double sc_time_stamp() { return 0; }`` or compile the Verilated code with
-code with :code:`-CFLAGS -DVL_TIME_CONTEXT`.
+``-CFLAGS -DVL_TIME_CONTEXT``.
 
-Before Verilator 4.200, the :code:`sc_time_stamp()` function needs to be
+Before Verilator 4.200, the ``sc_time_stamp()`` function needs to be
 defined in C++ (non SystemC) to return the current simulation time.
 
 
 Why do I get "undefined reference to \`VL_RAND_RESET_I' or \`Verilated::...'"?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-You need to link your compiled Verilated code against the
+You need to link your compiled Verilated code against the ``verilated.cpp``
-:code:`verilated.cpp` file found in the include directory of the Verilator
+file found in the include directory of the Verilator kit. This is one
-kit.  This is one target in the ``$(VK_GLOBAL_OBJS)`` make variable, which
+target in the ``$(VK_GLOBAL_OBJS)`` make variable, which should be part of
-should be part of your Makefile's link rule.  If you use :vlopt:`--exe` or
+your Makefile's link rule. If you use :vlopt:`--exe` or :vlopt:`--binary`,
-:vlopt:`--binary`, this is done for you.
+this is done for you.
 
 
 Is the PLI supported?
@@ -370,8 +365,8 @@ also use the "import DPI" SystemVerilog feature to call C code (see the
 chapter above). There is also limited VPI access to public signals.
 
 If you want something more complex, since Verilator emits standard C++
-code, you can write C++ routines that can access and modify signal
+code, you can write C++ routines that can access and modify signal values
-values without needing any PLI interface code, and call it with
+without needing any PLI interface code, and call it with
 $c("{any_c++_statement}").
 
 See the :ref:`Connecting` section.
@@ -380,8 +375,8 @@ See the :ref:`Connecting` section.
 How do I make a Verilog module that contains a C++ object?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-You need to add the object to the structure Verilator creates, then
+You need to add the object to the structure Verilator creates, then use $c
-use $c to call a method inside your object.  The
+to call a method inside your object. The
 :file:`test_regress/t/t_extend_class` files in the distribution show an
 example of how to do this.
 
@@ -402,14 +397,14 @@ How do I get faster build times?
 * Use a recent compiler. Newer compilers tend to be faster.
 
 * Compile in parallel on many machines and use caching; see the web for the
-  ccache, sccache, distcc, or icecream packages. ccache will skip GCC runs between
+  ccache, sccache, distcc, or icecream packages. ccache will skip GCC runs
-  identical source builds, even across different users.  If ccache was
+  between identical source builds, even across different users. If ccache
-  installed when Verilator was built, it is used, or see OBJCACHE
+  was installed when Verilator was built, it is used, or see OBJCACHE
   environment variable to override this. Also see the
   :vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`.
 
-* To reduce the compile time of classes that use a Verilated module (e.g., a
+* To reduce the compile time of classes that use a Verilated module (e.g.,
-  top CPP file) you may wish to add a
+  a top CPP file) you may wish to add a
   :option:`/*verilator&32;no_inline_module*/` metacomment to your top-level
   module. This will decrease the amount of code in the model's Verilated
   class, improving compile times of any instantiating top-level C++ code,
@@ -422,9 +417,9 @@ Why do so many files need to recompile when I add a signal?
 """""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
 Adding a new signal requires the symbol table to be recompiled. Verilator
-uses one large symbol table, resulting in 2-3 fewer assembly
+uses one large symbol table, resulting in 2-3 fewer assembly instructions
-instructions for each signal access.  This makes the execution time 10-15%
+for each signal access. This makes the execution time 10-15% faster, but
-faster, but can result in more compilations when something changes.
+can result in more compilations when something changes.
 
 
 How do I access Verilog functions/tasks in C?
@@ -450,8 +445,8 @@ How do I access signals in C?
 
 The best thing to do is to make a SystemVerilog "export DPI" task or
 function that accesses that signal, as described in the DPI chapter in the
-manual and DPI tutorials on the web.  This will allow Verilator to
+manual and DPI tutorials on the web. This will allow Verilator to optimize
-optimize the model better and should be portable across simulators.
+the model better and should be portable across simulators.
 
 If you really want raw access to the signals, declare the signals you will
 be accessing with a :option:`/*verilator&32;public*/` metacomment before
@@ -461,29 +456,28 @@ the signal, as you would any other member variable.
 Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t),
 16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or
 64-bit unsigned long longs (uint64_t) that fit the width of the signal.
-Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for
+Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for 1
-1 to 64 bits, and the compiler will properly up-convert smaller entities.
+to 64 bits, and the compiler will properly up-convert smaller entities.
 Note that even signed ports are declared as unsigned; you must sign extend
 yourself to the appropriate signal width.
 
 Signals wider than 64 bits are stored as an array of 32-bit uint32_t's.
 Thus, to read bits 31:0, access signal[0], and for bits 63:32, access
 signal[1]. Unused bits (for example, bit numbers 65-96 of a 65-bit vector)
-will always be zero.  If you change the value, you must pack
+will always be zero. If you change the value, you must pack zeros in the
-zeros in the unused bits, or core-dumps may result because Verilator strips
+unused bits, or core-dumps may result because Verilator strips array bound
-array bound checks where it believes them to be unnecessary to improve
+checks where it believes them to be unnecessary to improve performance.
-performance.
 
 In the SYSTEMC example above, if you had in our.v:
 
- .. code-block:: sv
+.. code-block:: sv
 
    input clk /*verilator public*/;
    // Note the placement of the semicolon above
 
 From the sc_main.cpp file, you'd then:
 
- .. code-block:: C++
+.. code-block:: C++
 
    #include "Vour.h"
    #include "Vour_our.h"
@@ -498,10 +492,10 @@ clocks, or you'll get strange results.
 Should a module be in Verilog or SystemC?
 """""""""""""""""""""""""""""""""""""""""
 
-Sometimes there is a block that only interconnects instances, and you have a
+Sometimes there is a block that only interconnects instances, and you have
-choice if you write it in Verilog or SystemC.  Everything else being
+a choice if you write it in Verilog or SystemC. Everything else being
-equal, the best performance is when Verilator sees all of the design.  So, look
+equal, the best performance is when Verilator sees all of the design. So,
-at the hierarchy of your design, labeling instances as to if they are
+look at the hierarchy of your design, labeling instances as to if they are
 SystemC or Verilog. Then:
 
 * A module with only SystemC instances below must be SystemC.
@@ -511,6 +505,6 @@ SystemC or Verilog.  Then:
 
 * A module with only Verilog instances below can be either, but for best
   performance should be Verilog. (The exception is if you have a design
-  that is instantiated many times; in this case, Verilating one of the lower
+  that is instantiated many times; in this case, Verilating one of the
-  modules and instantiating that Verilated instances multiple times into a
+  lower modules and instantiating that Verilated instances multiple times
-  SystemC module *may* be faster.)
+  into a SystemC module *may* be faster.)

docs/guide/files.rst

@@ -1,11 +1,11 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *****
 Files
 *****
 
-.. _Files in the Distribution:
+.. _files in the distribution:
 
 Files in the Git Tree
 =====================
@@ -28,7 +28,7 @@ Verilator:
    test_regress                => Internal tests
 
 
-.. _Files Read/Written:
+.. _files read/written:
 
 Files Read/Written
 ==================
@@ -42,33 +42,33 @@ For --cc/--sc, it creates:
 
 .. list-table::
 
-   * - *{prefix}*\ .json
+   * - *{prefix}*.json
      - JSON build definition compiling (from --make json)
-   * - *{prefix}*\ .mk
+   * - *{prefix}*.mk
      - Make include file for compiling (from --make gmake)
    * - *{prefix}*\ _classes.mk
      - Make include file with class names (from --make gmake)
-   * - *{prefix}*\ .h
+   * - *{prefix}*.h
      - Model header
-   * - *{prefix}*\ .cpp
+   * - *{prefix}*.cpp
      - Model C++ file
    * - *{prefix}*\ ___024root.h
      - Top-level internal header file (from SystemVerilog $root)
    * - *{prefix}*\ ___024root.cpp
      - Top-level internal C++ file (from SystemVerilog $root)
-   * - *{prefix}*\ ___024root\ *{__n}*\ .cpp
+   * - *{prefix}*\ ___024root\ *{__n}*.cpp
      - Additional top-level internal C++ files
-   * - *{prefix}*\ ___024root__Slow\ *{__n}*\ .cpp
+   * - *{prefix}*\ ___024root__Slow\ *{__n}*.cpp
      - Infrequent cold routines
-   * - *{prefix}*\ ___024root__Trace\ *{__n}*\ .cpp
+   * - *{prefix}*\ ___024root__Trace\ *{__n}*.cpp
      - Wave file generation code (from --trace-\*)
-   * - *{prefix}*\ ___024root__Trace__Slow\ *{__n}*\ .cpp
+   * - *{prefix}*\ ___024root__Trace__Slow\ *{__n}*.cpp
      - Wave file generation code (from --trace-\*)
    * - *{prefix}*\ __Dpi.h
      - DPI import and export declarations (from --dpi)
    * - *{prefix}*\ __Dpi.cpp
      - Global DPI export wrappers (from --dpi)
-   * - *{prefix}*\ __Dpi_Export\ *{__n}*\ .cpp
+   * - *{prefix}*\ __Dpi_Export\ *{__n}*.cpp
      - DPI export wrappers scoped to this particular model (from --dpi)
    * - *{prefix}*\ __Inlines.h
      - Inline support functions
@@ -76,11 +76,11 @@ For --cc/--sc, it creates:
      - Global symbol table header
    * - *{prefix}*\ __Syms.cpp
      - Global symbol table C++
-   * - *{prefix}{each_verilog_module}*\ .h
+   * - *{prefix}{each_verilog_module}*.h
      - Lower level internal header files
-   * - *{prefix}{each_verilog_module}*\ .cpp
+   * - *{prefix}{each_verilog_module}*.cpp
      - Lower level internal C++ files
-   * - *{prefix}{each_verilog_module}{__n}*\ .cpp
+   * - *{prefix}{each_verilog_module}{__n}*.cpp
      - Additional lower C++ files
 
 For --hierarchical mode, it creates:
@@ -106,13 +106,13 @@ In specific debug and other modes, it also creates:
 
 .. list-table::
 
-   * - *{prefix}*\ .sarif
+   * - *{prefix}*.sarif
      - SARIF diagnostics (from --diagnostics-sarif)
-   * - *{prefix}*\ .tree.json
+   * - *{prefix}*.tree.json
      - JSON tree information (from --json-only)
-   * - *{prefix}*\ .tree.meta.json
+   * - *{prefix}*.tree.meta.json
      - JSON tree metadata (from --json-only)
-   * - *{prefix}*\ .xml
+   * - *{prefix}*.xml
      - XML tree information (from --xml)
    * - *{prefix}*\ __cdc.txt
      - Clock Domain Crossing checks (from --cdc)
@@ -124,30 +124,30 @@ In specific debug and other modes, it also creates:
      - Make dependencies (from -MMD)
    * - *{prefix}*\ __verFiles.dat
      - Timestamps (from --skip-identical)
-   * - *{prefix}{misc}*\ .dot
+   * - *{prefix}{misc}*.dot
      - Debugging graph files (from --debug)
-   * - *{prefix}{misc}*\ .tree
+   * - *{prefix}{misc}*.tree
      - Debugging files (from --debug)
-   * - *{prefix}*\ __inputs\ .vpp
+   * - *{prefix}*\ __inputs.vpp
      - Pre-processed verilog for all files (from --debug)
-   * - *{prefix}*\ _ *{each_verilog_base_filename}*\ .vpp
+   * - *{prefix}*\ _ *{each_verilog_base_filename}*.vpp
      - Pre-processed verilog for each file (from --debug)
 
 After running Make, the C++ compiler may produce the following:
 
 .. list-table::
 
-   * - verilated{misc}*\ .d
+   * - verilated{misc}*.d
      - Intermediate dependencies
-   * - verilated{misc}*\ .o
+   * - verilated{misc}*.o
      - Intermediate objects
-   * - {mod_prefix}{misc}*\ .d
+   * - {mod_prefix}{misc}*.d
      - Intermediate dependencies
-   * - {mod_prefix}{misc}*\ .o
+   * - {mod_prefix}{misc}*.o
      - Intermediate objects
    * - *{prefix}*\
      - Final executable (from --exe)
-   * - lib\ *{prefix}*\ .a
+   * - lib\ *{prefix}*.a
      - Final archive (default lib mode)
    * - libverilated.a
      - Runtime for verilated model (default lib mode)
@@ -155,9 +155,9 @@ After running Make, the C++ compiler may produce the following:
      - Library of all Verilated objects
    * - *{prefix}*\ __ALL.cpp
      - Include of all code for single compile
-   * - *{prefix}{misc}*\ .d
+   * - *{prefix}{misc}*.d
      - Intermediate dependencies
-   * - *{prefix}{misc}*\ .o
+   * - *{prefix}{misc}*.o
      - Intermediate objects
 
 The Verilated executable may produce the following:

docs/guide/index.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ######################

docs/guide/install-cmake.rst

@@ -1,36 +1,43 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _CMakeInstallation:
+.. _cmakeinstallation:
 
 ******************
 CMake Installation
 ******************
 
 This section discusses how to build and install Verilator using cmake.
-Currently cmake is only officially supported for Windows builds (not Linux).
+Currently cmake is only officially supported for Windows builds (not
+Linux).
 
-.. _Tools Install:
+.. _tools install:
 
 Quick Install
 =============
 
 1. Install Python for your platform from https://www.python.org/downloads/.
-2. Install CMake for your platform from https://cmake.org/download/ or build it from source.
+2. Install CMake for your platform from https://cmake.org/download/ or
-3. If the compiler of your choice is MSVC, then install https://visualstudio.microsoft.com/downloads/.
+   build it from source.
-   If the compiler of your choice is Clang, then install https://releases.llvm.org/download.html or build it from source.
+3. If the compiler of your choice is MSVC, then install
-4. For flex and bison use https://github.com/lexxmark/winflexbison to build and install.
+   https://visualstudio.microsoft.com/downloads/. If the compiler of your
-5. For build on Windows using MSVC set environment variable WIN_FLEX_BISON to install directory.
+   choice is Clang, then install https://releases.llvm.org/download.html or
-   For build on Windows/Linux/OS-X using ninja set the environment variable
+   build it from source.
-   FLEX_INCLUDE to the directory containing FlexLexer.h and ensure that flex/bison
+4. For flex and bison use https://github.com/lexxmark/winflexbison to build
-   is available within the PATH.
+   and install.
+5. For build on Windows using MSVC set environment variable WIN_FLEX_BISON
+   to install directory. For build on Windows/Linux/OS-X using ninja set
+   the environment variable FLEX_INCLUDE to the directory containing
+   FlexLexer.h and ensure that flex/bison is available within the PATH.
 
-To obtain verilator sources download https://github.com/verilator/verilator/archive/refs/heads/master.zip
+To obtain Verilator sources download
-or clone https://github.com/verilator/verilator using git :ref:`Obtain Sources`.
+https://github.com/verilator/verilator/archive/refs/heads/master.zip or
+clone https://github.com/verilator/verilator using git :ref:`Obtain
+Sources`.
 
 To build using MSVC:
 
-::
+.. code-block:: bash
 
    cd verilator  # directory containing source files of verilator
    mkdir build
@@ -38,10 +45,9 @@ To build using MSVC:
    cmake --build . --config Release
    cmake --install . --prefix $PWD/../install
 
-
 To build using ninja:
 
-::
+.. code-block:: bash
 
    cd verilator
    mkdir build
@@ -50,7 +56,7 @@ To build using ninja:
    cmake --install . --prefix $PWD/../install
 
 
-.. _CMake Usage:
+.. _cmake usage:
 
 Usage
 =====
@@ -61,7 +67,7 @@ install directory specified in the above build.
 Example
 =======
 
-::
+.. code-block:: bash
 
    cd verilator/examples
    cd cmake_hello_c

docs/guide/install.rst

@@ -1,7 +1,7 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Installation:
+.. _installation:
 
 ************
 Installation
@@ -9,15 +9,15 @@ Installation
 
 This section discusses how to install Verilator.
 
-.. _Package Manager Quick Install:
+.. _package manager quick install:
 
 Package Manager Quick Install
 =============================
 
-Using a distribution's package manager is the easiest way to get
+Using a distribution's package manager is the easiest way to get started.
-started. (Note distribution packages almost never have the most recent
+(Note distribution packages almost never have the most recent Verilator
-Verilator version, so we recommend following :ref:`Git Install` below,
+version, so we recommend following :ref:`Git Install` below, instead.) To
-instead.) To install as a package:
+install as a package:
 
 .. code-block:: bash
 
@@ -26,17 +26,18 @@ instead.) To install as a package:
 For other distributions, refer to `Repology Verilator Distro Packages
 <https://repology.org/project/verilator>`__.
 
-.. _pre-commit Quick Install:
+.. _pre-commit quick install:
 
-pre-commit Quick Install
+Pre-commit Quick Install
-=============================
+========================
 
 You can use Verilator's `pre-commit <https://pre-commit.com/>`__ hook to
 lint your code before committing it. It encapsulates the :ref:`Verilator
 Build Docker Container`, so you need docker on your system to use it. The
 verilator image will be downloaded automatically.
 
-To use the hook, add the following entry to your :code:`.pre-commit-config.yaml`:
+To use the hook, add the following entry to your
+``.pre-commit-config.yaml``:
 
 .. code-block:: yaml
 
@@ -46,7 +47,7 @@ To use the hook, add the following entry to your :code:`.pre-commit-config.yaml`
        hooks:
          - id: verilator
 
-.. _Git Install:
+.. _git install:
 
 Git Quick Install
 =================
@@ -83,7 +84,7 @@ In brief, to install from git:
    sudo make install
 
 
-.. _Detailed Build Instructions:
+.. _detailed build instructions:
 
 Detailed Build Instructions
 ===========================
@@ -129,15 +130,15 @@ For constraints:
 
    sudo apt-get install z3  # Optional solver
 
-The following is optional but is recommended for nicely rendered command line
+The following is optional but is recommended for nicely rendered command
-help when running Verilator:
+line help when running Verilator:
 
 .. code-block:: bash
 
    sudo apt-get install perl-doc
 
-To build or run Verilator, the following are optional but should be installed
+To build or run Verilator, the following are optional but should be
-for good performance:
+installed for good performance:
 
 .. code-block:: bash
 
@@ -152,22 +153,37 @@ need to be present to run Verilator:
 
    sudo apt-get install git autoconf flex bison
 
-Those developing Verilator itself also need these (see internals.rst):
+Those developing Verilator itself also need the following additional
+packages (see internals.rst), and a Python virtual environment:
 
 .. code-block:: bash
 
    sudo apt-get install clang clang-format-18 cmake gdb gprof graphviz lcov
-   sudo apt-get install python3-clang python3-distro pipx yapf3 bear jq
+   sudo apt-get install python3-clang bear jq
-   python3 -m venv --system-site-packages ~/.verilator_pyenv
-   source ~/.verilator_pyenv/bin/activate
-   pip3 install sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe gersemi mbake mypy ruff
-   pip3 install git+https://github.com/antmicro/astsee.git
-   pipx install sarif-tools
    cpan install Pod::Perldoc
-   #
-   # Later, when building or testing Verilator, you will need
-   source ~/.verilator_pyenv/bin/activate
 
+The Python virtual environment is only required for running the whole test
+suite, and for additional development steps like linting and formatting. It
+is not required for building Verilator itself. To install the python
+virtual environment and all dependencies automatically, run the following
+once, after ``configure``:
+
+.. code-block:: bash
+
+   # Create Python virutal environment in .venv:
+   make venv
+
+   # Or alternatively, to put it somewhere else:
+   make venv VENV_PATH=where_you_want_it
+
+Then activate the virtual environment in the shell using:
+
+.. code-block:: bash
+
+   source .venv/bin/activate
+
+   # Or if installed somewhere else:
+   source where_you_want_it/bin/activate
 
 Install SystemC
 ^^^^^^^^^^^^^^^
@@ -199,14 +215,14 @@ Install Z3
 ^^^^^^^^^^
 
 In order to use constrained randomization the `Z3 Theorem Prover
-<https://github.com/z3prover/z3>`__ must be installed, however this is
+<https://github.com/z3prover/z3>`__ must be installed, however this is not
-not required at Verilator build time. There are other compatible SMT solvers,
+required at Verilator build time. There are other compatible SMT solvers,
-like CVC5/CVC4, but they are not guaranteed to work. Since different solvers are
+like CVC5/CVC4, but they are not guaranteed to work. Since different
-faster for different scenarios, the solver to use at run-time can be specified
+solvers are faster for different scenarios, the solver to use at run-time
-by the environment variable :option:`VERILATOR_SOLVER`.
+can be specified by the environment variable :option:`VERILATOR_SOLVER`.
 
 
-.. _Obtain Sources:
+.. _obtain sources:
 
 Obtain Sources
 --------------
@@ -269,7 +285,7 @@ co-exist on a system.
    ./configure
    # Running will use files from $VERILATOR_ROOT, so no install needed
 
-Note after installing (see `Installation`_), a calling program or shell
+Note after installing (see ref:`Installation`), a calling program or shell
 must set the environment variable :option:`VERILATOR_ROOT` to point to this
 Git directory, then execute ``$VERILATOR_ROOT/bin/verilator``, which will
 find the path to all needed files.
@@ -291,7 +307,7 @@ location include the Verilator version name:
    # For the tarball, use the version number instead of git describe
    ./configure --prefix /CAD_DISK/verilator/`git describe | sed "s/verilator_//"`
 
-Note after installing (see `Installation`_), you need to add the path to
+Note after installing (see ref:`Installation`), you need to add the path to
 the ``bin`` directory to your ``PATH``. Or, if you use `modulecmd
 <https://modules.sourceforge.net/>`__, you'll want a module file like the
 following:
@@ -317,7 +333,7 @@ configure's default system paths:
    unsetenv VERILATOR_ROOT   # if your shell is csh
    ./configure
 
-Then after installing (see `Installation`_), the binaries should be in a
+Then after installing (see ref:`Installation`), the binaries should be in a
 location already in your ``$PATH`` environment variable.
 
 

docs/guide/languages.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ***************
@@ -77,8 +77,8 @@ Verilog AMS Support
 
 Verilator implements a very small subset of Verilog AMS (Verilog Analog and
 Mixed-Signal Extensions) with the subset corresponding to those VMS
-keywords with near-equivalents in Verilog IEEE 1364 or SystemVerilog
+keywords with near-equivalents in Verilog IEEE 1364 or SystemVerilog IEEE
-IEEE 1800.
+1800.
 
 AMS parsing is enabled with :vlopt:`--language VAMS <--language>` or
 :vlopt:`--language 1800+VAMS <--language>`.
@@ -90,10 +90,9 @@ wreal.
 Synthesis Directive Assertion Support
 -------------------------------------
 
-Verilator reads any :code:`//synopsys full_case` or :code:`//synopsys
+Verilator reads any ``//synopsys full_case`` or ``//synopsys
-parallel_case` directives.  The same applies to any :code:`//ambit
+parallel_case`` directives. The same applies to any ``//ambit synthesis``,
-synthesis`, :code:`//cadence` or :code:`//pragma` directives of the same
+``//cadence`` or ``//pragma`` directives of the same form.
-form.
 
 When these synthesis directives are discovered, unless
 :vlopt:`--no-assert-case` option is used, Verilator will either formally
@@ -115,17 +114,17 @@ With :vlopt:`--timing`, all timing controls are supported:
 * event control statements not only at the top of a process,
 * intra-assignment timing controls,
 * net delays,
-* :code:`wait` statements,
+* ``wait`` statements,
 
-as well as all flavors of :code:`fork`.
+as well as all flavors of ``fork``.
 
-Compiling a Verilated design that uses these features requires a
+Compiling a Verilated design that uses these features requires a compiler
-compiler with C++20 coroutine support, e.g. Clang 5, GCC 10, or newer.
+with C++20 coroutine support, e.g. Clang 5, GCC 10, or newer.
 
-:code:`#0` delays cause Verilator to issue the :option:`ZERODLY` warning, as
+``#0`` delays cause Verilator to issue the :option:`ZERODLY` warning, as
-they work differently than described in the LRM. They do not schedule process
+they work differently than described in the LRM. They do not schedule
-resumption in the Inactive region, though the process will get resumed in the
+process resumption in the Inactive region, though the process will get
-same time slot.
+resumed in the same time slot.
 
 Rising/falling/turn-off delays are currently unsupported and cause the
 :option:`RISEFALLDLY` warning.
@@ -135,8 +134,8 @@ is always the one chosen. Such expressions cause the :option:`MINTYPMAXDLY`
 warning.
 
 Another consequence of using :vlopt:`--timing` is that the :vlopt:`--main`
-option generates a main file with a proper timing eval loop, eliminating the
+option generates a main file with a proper timing eval loop, eliminating
-need for writing any driving C++ code. You can simply compile the
+the need for writing any driving C++ code. You can simply compile the
 simulation (perhaps using :vlopt:`--build`) and run it.
 
 With :vlopt:`--no-timing`, all timing controls cause the :option:`NOTIMING`
@@ -144,15 +143,15 @@ error, except:
 
 * delay statements - they are ignored (as they are in synthesis), though they
   do issue a :option:`STMTDLY` warning,
-* intra-assignment timing controls - they are ignored, though they do issue an
+* intra-assignment timing controls - they are ignored, though they do issue
-  :option:`ASSIGNDLY` warning,
+  an :option:`ASSIGNDLY` warning,
 * net delays - they are ignored,
 * event controls at the top of the procedure,
 
 Forks cause this error as well, except:
 
 * forks with no statements,
-* :code:`fork..join` or :code:`fork..join_any` with one statement,
+* ``fork..join`` or ``fork..join_any`` with one statement,
 * forks with :vlopt:`--bbox-unsup`.
 
 If neither :vlopt:`--timing` nor :vlopt:`--no-timing` is specified, all
@@ -160,19 +159,19 @@ timing controls cause the :option:`NEEDTIMINGOPT` error, except event
 controls at the top of the process. Forks cause this error as well, except:
 
 * forks with no statements,
-* :code:`fork..join` or :code:`fork..join_any` with one statement,
+* ``fork..join`` or ``fork..join_any`` with one statement,
 * forks with :vlopt:`--bbox-unsup`.
 
 Timing controls and forks can also be ignored in specific files or parts of
 files. The :option:`/*verilator&32;timing_off*/` and
-:option:`/*verilator&32;timing_off*/` metacomments will make Verilator ignore
+:option:`/*verilator&32;timing_off*/` metacomments will make Verilator
-the encompassed timing controls and forks, regardless of the chosen
+ignore the encompassed timing controls and forks, regardless of the chosen
 :vlopt:`--timing` or :vlopt:`--no-timing` option. This can also be achieved
-using the :option:`timing_off` and :option:`timing_off` options in Verilator
+using the :option:`timing_off` and :option:`timing_off` options in
-Control Files.
+Verilator Control Files.
 
 
-.. _Language Limitations:
+.. _language limitations:
 
 Language Limitations
 ====================
@@ -193,28 +192,28 @@ Compiler would, namely given a block of the form:
 
 This will recompute y when there is a potential for change in x or a change
 in z; that is when the flops computing x or z evaluate (which is what
-Design Compiler will synthesize.)  A compliant simulator will only
+Design Compiler will synthesize.) A compliant simulator will only calculate
-calculate y if x changes.  We recommend using always_comb to make the code
+y if x changes. We recommend using always_comb to make the code run the
-run the same everywhere.  Also avoid putting $displays in combo blocks, as
+same everywhere. Also avoid putting $displays in combo blocks, as they may
-they may print multiple times when not desired, even on compliant
+print multiple times when not desired, even on compliant simulators as
-simulators as event ordering is not specified.
+event ordering is not specified.
 
 
 Signal Naming
 -------------
 
 To avoid conflicts with C symbol naming, any character in a signal name
-that is not alphanumeric nor a single underscore will be replaced by __0hh
+that is not alphanumeric nor a single underscore will be replaced by
-where hh is the hex code of the character. To avoid conflicts with
+`__0hh` where `hh` is the hex code of the character. To avoid conflicts
-Verilator's internal symbols, any double underscore is replaced with
+with Verilator's internal symbols, any double underscore is replaced with
-___05F (5F is the hex code of an underscore.)
+`___05F` (5F is the hex code of an underscore.)
 
 
 Bind
 ----
 
-Verilator only supports bind to a target module name, not to an
+Verilator only supports bind to a target module name, not to an instance
-instance path.
+path.
 
 
 Class
@@ -254,7 +253,7 @@ generating one member of a structure from blocking, and another from
 non-blocking assignments is unsupported.
 
 
-.. _Unknown States:
+.. _unknown states:
 
 Unknown States
 --------------
@@ -265,24 +264,23 @@ However, it has two features that uncover most initialization bugs
 
 Identity comparisons (=== or !==) are converted to standard ==/!= when
 neither side is a constant. This may make the expression yield a different
-result than a four-state simulator.  An === comparison to X will
+result than a four-state simulator. An === comparison to X will always be
-always be false, so that Verilog code which checks for uninitialized logic
+false, so that Verilog code which checks for uninitialized logic will not
-will not fire.
+fire.
 
 Assigning X to a variable will assign a constant value as determined by the
-:vlopt:`--x-assign` option.  This allows runtime randomization; thus, if
+:vlopt:`--x-assign` option. This allows runtime randomization; thus, if the
-the value is used, the random value should cause downstream errors.
+value is used, the random value should cause downstream errors. Integers
-Integers also get randomized, even though the Verilog 2001 specification
+also get randomized, even though the Verilog 2001 specification says they
-says they initialize to zero.  However, randomization happens at
+initialize to zero. However, randomization happens at initialization time;
-initialization time; hence, during a single simulation run, the same
+hence, during a single simulation run, the same constant (but random) value
-constant (but random) value will be used every time the assignment is
+will be used every time the assignment is executed.
-executed.
 
 All variables, depending on :vlopt:`--x-initial` setting, are typically
 randomly initialized using a function. You can determine that reset is
 working correctly by running several random simulation runs. On the first
-run, have the function initialize variables to zero.  On the second, have
+run, have the function initialize variables to zero. On the second, have it
-it initialize variables to one.  On the third and following runs, have it
+initialize variables to one. On the third and following runs, have it
 initialize them randomly. If the results match, reset works. (Note that
 this is what the hardware will do.) In practice, setting all variables to
 one at startup finds the most problems (since control signals are typically
@@ -304,8 +302,7 @@ Tri/Inout
 
 Verilator converts some simple tristate structures into two state. Pullup,
 pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are
-also supported.  Simple comparisons with :code:`=== 1'bz` are also
+also supported. Simple comparisons with ``=== 1'bz`` are also supported.
-supported.
 
 An assignment of the form:
 
@@ -372,20 +369,20 @@ Assertions
 ----------
 
 Verilator is beginning to add support for assertions. Verilator currently
-only converts assertions to simple :code:`if (...) error` statements, and
+only converts assertions to simple ``if (...) error`` statements, and
 coverage statements to increment the line counters described in the
 coverage section.
 
-Verilator does not support SEREs yet.  All assertion and coverage
+Verilator does not support SEREs yet. All assertion and coverage statements
-statements must be simple expressions that complete in one cycle.
+must be simple expressions that complete in one cycle.
 
 
 Encrypted Verilog
 -----------------
 
-Open-source simulators like Verilator cannot use encrypted RTL
+Open-source simulators like Verilator cannot use encrypted RTL (i.e. IEEE
-(i.e. IEEE P1735).  Talk to your IP vendor about delivering IP blocks via
+P1735). Talk to your IP vendor about delivering IP blocks using Verilator's
-Verilator's :vlopt:`--protect-lib` feature.
+:vlopt:`--protect-lib` feature.
 
 
 Language Keyword Limitations
@@ -394,6 +391,7 @@ Language Keyword Limitations
 This section describes specific limitations for each language keyword.
 
 .. Hack to get long definition list:
+
 .. |cmdslong1| replace:: \`__FILE__, \`__LINE__, \`begin_keywords,
    \`begin_keywords, \`begin_keywords, \`begin_keywords, \`begin_keywords,
    \`define, \`else, \`elsif, \`end_keywords, \`endif, \`error, \`ifdef,
@@ -404,7 +402,6 @@ This section describes specific limitations for each language keyword.
 |cmdslong1|
    Fully supported.
 
-
 .. Hack to get long definition list:
 
 .. |cmdslong2| replace:: always, always_comb, always_ff, always_latch, and,
@@ -424,9 +421,10 @@ This section describes specific limitations for each language keyword.
    certain limited cases.
 
 '{} operator
-  Assignment patterns with an order based, default, constant integer (array)
+   Assignment patterns with an order based, default, constant integer
-  or member identifier (struct/union) keys are supported.  Data type keys
+   (array) or member identifier (struct/union) keys are supported. Data
-  and keys computed from a constant expression are not supported.
+   type keys and keys computed from a constant expression are not
+   supported.
 
 \`uselib
    Uselib, a vendor-specific library specification method, is ignored along
@@ -456,8 +454,8 @@ force, release
    entirely comply with IEEE 1800-2023:
 
    #. Using forced variable as a value to another force statement is
-     currently not supported. The dependent force statement is forced by an
+      currently not supported. The dependent force statement is forced by
-     initial constant value.
+      an initial constant value.
 
    #. Force/release with procedural continuous assignment is not supported.
       The assignment is treated as procedural.
@@ -470,9 +468,9 @@ inside
    upper bound. Case inside and case matches are also unsupported.
 
 interface
-  Interfaces and modports, including generated data types are
+   Interfaces and modports, including generated data types are supported.
-  supported.  Generate blocks around modports are not supported, nor are
+   Generate blocks around modports are not supported, nor are virtual
-  virtual interfaces nor unnamed interfaces.
+   interfaces nor unnamed interfaces.
 
 shortreal
    Short floating point (shortreal) numbers are converted to real. Most
@@ -490,28 +488,28 @@ $bits, $countbits, $countones, $finish, $isunknown, $onehot, $onehot0, $signed,
    Generally supported.
 
 $dump/$dumpports and related
-  $dumpfile or $dumpports will create a VCD or FST file (based on
+   $dumpfile or $dumpports will create a VCD or FST file (based on the
-  the :vlopt:`--trace-vcd` option given when the model was Verilated). This
+   :vlopt:`--trace-vcd` option given when the model was Verilated). This
    will take effect starting at the next eval() call. If you have multiple
-  Verilated designs under the same C model, this will dump signals
+   Verilated designs under the same C model, this will dump signals only
-  only from the design containing the $dumpvars.
+   from the design containing the $dumpvars.
 
    $dumpvars and $dumpports module identifier is ignored; the traced
-  instances will always start at the top of the design. The levels argument
+   instances will always start at the top of the design. The levels
-  is also ignored; use tracing_on/tracing_off pragmas instead.
+   argument is also ignored; use tracing_on/tracing_off pragmas instead.
 
    $dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename
    argument is ignored; only a single trace file may be active at once.
 
-  $dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and
+   $dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff,
-  $dumplimit/$dumpportlimit are currently ignored.
+   and $dumplimit/$dumpportlimit are currently ignored.
 
 $error, $fatal, $info, $warning.
    Generally supported.
 
 $exit, $finish, $stop
-  The rarely used optional parameter to $finish and $stop is ignored; $exit
+   The rarely used optional parameter to $finish and $stop is ignored;
-  is aliased to $finish.
+   $exit is aliased to $finish.
 
 $fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite, $fscanf, $sscanf
    Generally supported.

docs/guide/overview.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ********
@@ -42,10 +42,10 @@ The best place to get started is to try the :ref:`Examples`.
 
 
 .. [#] Verilog is defined by the `Institute of Electrical and Electronics
-       Engineers (IEEE) Standard for Verilog Hardware Description
+   Engineers (IEEE) Standard for Verilog Hardware Description Language`,
-       Language`, Std. 1364, released in 1995, 2001, and 2005.  The
+   Std. 1364, released in 1995, 2001, and 2005. The Verilator documentation
-       Verilator documentation uses the shorthand, e.g., "IEEE 1364-2005",
+   uses the shorthand, e.g., "IEEE 1364-2005", to refer to the, e.g., 2005
-       to refer to the, e.g., 2005 version of this standard.
+   version of this standard.
 
 .. [#] SystemVerilog is defined by the `Institute of Electrical and
    Electronics Engineers (IEEE) Standard for SystemVerilog - Unified

docs/guide/simulating.rst

@@ -1,7 +1,7 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Simulating:
+.. _simulating:
 
 ************************************
 Simulating (Verilated-Model Runtime)
@@ -12,7 +12,7 @@ Verilated model's executable.  For the runtime arguments to a simulated
 model, see :ref:`Simulation Runtime Arguments`.
 
 
-.. _Simulation Summary Report:
+.. _simulation summary report:
 
 Simulation Summary Report
 =========================
@@ -49,8 +49,8 @@ The information in this report is:
 
    Simulated time (if non-zero) divided by wall time. e.g. `123 ns/s` means
    123 simulated nanoseconds took 1 second of wall time; for a model with
-   only a 1 GHz clock that would be equivalent to 123.1 cycles per
+   only a 1 GHz clock that would be equivalent to 123.1 cycles per second.
-   second. The units are automatically selected to give a number between 1
+   The units are automatically selected to give a number between 1
    and 1000. The wall time includes initialization, initial and final
    process blocks, so indicates a slower speed than if the model had a
    longer runtime.
@@ -68,22 +68,20 @@ The information in this report is:
    Total memory used during simulation in megabytes.
 
 
-.. _Benchmarking & Optimization:
+.. _benchmarking & optimization:
 
 Benchmarking & Optimization
 ===========================
 
 For best performance, run Verilator with the :vlopt:`-O3`
-:vlopt:`--x-assign fast <--x-assign>`
+:vlopt:`--x-assign fast <--x-assign>` :vlopt:`--x-initial fast
-:vlopt:`--x-initial fast <--x-initial>`
+<--x-initial>` :vlopt:`--no-assert` options. The :vlopt:`-O3` option will
-:vlopt:`--no-assert` options.  The :vlopt:`-O3`
+require a longer time to run Verilator, and :vlopt:`--x-assign fast
-option will require a longer time to run Verilator, and
+<--x-assign>` :vlopt:`--x-initial fast <--x-assign>` may increase the risk
-:vlopt:`--x-assign fast <--x-assign>`
+of reset bugs in trade for performance. The :vlopt:`--no-assert` will
-:vlopt:`--x-initial fast <--x-assign>`
+suppress checking assertions, which is faster and appropriate for
-may increase the risk of reset bugs in trade for performance.  The
+known-good models running software, but may hide design errors. See the
-:vlopt:`--no-assert` will suppress checking assertions, which is faster and
+above documentation for these options.
-appropriate for known-good models running software, but may hide design
-errors.  See the above documentation for these options.
 
 If using Verilated multithreaded, consider overriding Verilator's default
 thread-to-processor assignment by using ``numactl``; see
@@ -110,12 +108,12 @@ example:
 
    make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a
 
-OPT_FAST specifies optimization options for those parts of the model
+OPT_FAST specifies optimization options for those parts of the model on the
-on the fast path. This is mostly code that is executed every
+fast path. This is mostly code that is executed every cycle. OPT_SLOW
-cycle. OPT_SLOW applies to slow-path code, which rarely executes, often
+applies to slow-path code, which rarely executes, often only once at the
-only once at the beginning or end of the simulation. OPT_SLOW is
+beginning or end of the simulation. OPT_SLOW is ignored if
-ignored if VM_PARALLEL_BUILDS is not 1, in which case all generated code
+VM_PARALLEL_BUILDS is not 1, in which case all generated code will be
-will be compiled in a single compilation unit using OPT_FAST. See also the
+compiled in a single compilation unit using OPT_FAST. See also the
 Verilator :vlopt:`--output-split` option. The OPT_GLOBAL variable applies
 to common code in the runtime library used by Verilated models (shipped in
 $VERILATOR_ROOT/include). Additional C++ files passed on the verilator
@@ -174,7 +172,7 @@ keep tabs on how Verilator compares and may be able to suggest additional
 improvements.
 
 
-.. _Coverage Analysis:
+.. _coverage analysis:
 
 Coverage Analysis
 =================
@@ -183,15 +181,15 @@ Verilator supports adding code to the Verilated model to support
 SystemVerilog code coverage. With :vlopt:`--coverage`, Verilator enables
 all forms of coverage:
 
-* :ref:`User Coverage`
+- :ref:`User Coverage`
-* :ref:`Line Coverage`
+- :ref:`Line Coverage`
-* :ref:`Toggle Coverage`
+- :ref:`Toggle Coverage`
 
 When a model with coverage is executed, it will create a coverage file for
 collection and later analysis, see :ref:`Coverage Collection`.
 
 
-.. _User Coverage:
+.. _user coverage:
 
 Functional Coverage
 -------------------
@@ -208,15 +206,15 @@ point under the coverage name "DefaultClock":
    DefaultClock: cover property (@(posedge clk) cyc==3);
 
 
-.. _Line Coverage:
+.. _line coverage:
 
 Line Coverage
 -------------
 
 With :vlopt:`--coverage` or :vlopt:`--coverage-line`, Verilator will
 automatically add coverage analysis at each code flow change point (e.g.,
-at branches).  At each such branch, a counter is incremented.  At the end
+at branches). At each such branch, a counter is incremented. At the end of
-of a test, the counters, filename, and line number corresponding to each
+a test, the counters, filename, and line number corresponding to each
 counter are written into the coverage file.
 
 Verilator may over-count combinatorial (non-clocked) blocks when those
@@ -225,7 +223,7 @@ disabled; for the most accurate results, do not disable this warning when
 using coverage.
 
 
-.. _Toggle Coverage:
+.. _toggle coverage:
 
 Toggle Coverage
 ---------------
@@ -251,10 +249,10 @@ separately.
 Verilator makes a minimally-intelligent decision about what clock domain
 the signal goes to, and only looks for edges in that clock domain. This
 means that edges may be ignored if it is known that the receiving logic
-could never see the edge.  This algorithm may improve in the future. The
+could never see the edge. This algorithm may improve in the future. The net
-net result is that coverage may be lower than what would be seen by looking
+result is that coverage may be lower than what would be seen by looking at
-at traces, but the coverage is a more accurate representation of the
+traces, but the coverage is a more accurate representation of the quality
-quality of stimulus into the design.
+of stimulus into the design.
 
 There may be edges counted near time zero while the model stabilizes. It's
 a good practice to zero all coverage just before releasing reset to prevent
@@ -265,7 +263,7 @@ A :option:`/*verilator&32;coverage_off*/`
 signals that do not need toggle analysis, such as RAMs and register files.
 
 
-.. _Expression Coverage:
+.. _expression coverage:
 
 Expression Coverage
 -------------------
@@ -284,12 +282,12 @@ Some expressions may produce too many cover points.  Verilator limits the
 maximum number of cover points per expression to 32, but this may be
 controlled with :vlopt:`--coverage-expr-max`.
 
-Below is an example showing expression coverage produced from `verilator_coverage`
+Below is an example showing expression coverage produced from
-as applied to the condition expression inside an if statement.  Each line
+`verilator_coverage` as applied to the condition expression inside an if
-shows the minimum number of terms and their values (e.g. `(t1==0 && t2==1)`) needed
+statement. Each line shows the minimum number of terms and their values
-to reach a result for the overall expression (e.g. `=> 1`).  Each line also
+(e.g. `(t1==0 && t2==1)`) needed to reach a result for the overall
-shows the number of times this combination was hit.  Note that individual lines
+expression (e.g. `=> 1`). Each line also shows the number of times this
-are not mutually exclusive.
+combination was hit. Note that individual lines are not mutually exclusive.
 
 .. code-block::
 
@@ -301,7 +299,7 @@ are not mutually exclusive.
    -000003  point: comment=(t2==0 && t4==0) => 0 hier=top.t
    -000002  point: comment=(t3==0 && t4==1) => 1 hier=top.t
 
-.. _Suppressing Coverage:
+.. _suppressing coverage:
 
 Suppressing Coverage
 --------------------
@@ -317,7 +315,7 @@ that should not occur.  A :option:`/*verilator&32;coverage_block_off*/`
 metacomment will perform a similar function on any code in that block or
 below.
 
-.. _Coverage Collection:
+.. _coverage collection:
 
 Coverage Collection
 -------------------
@@ -332,17 +330,17 @@ To get the coverage data from the model, write the coverage with either:
    :vlopt:`+verilator+coverage+file+\<filename\>`.
 
 2. In the user wrapper code, typically at the end once a test passes, call
-   :code:`Verilated::threadContextp()->coveragep()->write` with an argument
+   ``Verilated::threadContextp()->coveragep()->write`` with an argument of
-   of the filename for the coverage data file to write coverage data to
+   the filename for the coverage data file to write coverage data to
    (typically "logs/coverage.dat").
 
 Run each of your tests in different directories, potentially in parallel.
-Each test will create the file specified above,
+Each test will create the file specified above, e.g.
-e.g. :file:`logs/coverage.dat`.
+:file:`logs/coverage.dat`.
 
 After running all of the tests, execute the :command:`verilator_coverage`
-command, passing arguments pointing to the filenames of all the
+command, passing arguments pointing to the filenames of all the individual
-individual coverage files.  :command:`verilator_coverage` will read the
+coverage files. :command:`verilator_coverage` will read the
 :file:`logs/coverage.dat` file(s), and create an annotated source code
 listing showing code coverage details.
 
@@ -357,12 +355,11 @@ Additional options of :command:`verilator_coverage` allow for the merging
 of coverage data files or other transformations.
 
 Info files can be written by verilator_coverage for import to
-:command:`lcov`.  This enables using :command:`genhtml` for HTML reports
+:command:`lcov`. This enables using :command:`genhtml` for HTML reports and
-and importing reports to sites such as `https://codecov.io
+importing reports to sites such as https://codecov.io.
-<https://codecov.io>`_.
 
 
-.. _Profiling:
+.. _profiling:
 
 Code Profiling
 ==============
@@ -387,13 +384,13 @@ To use profiling:
    on which most of the time is being spent.
 
 
-.. _Execution Profiling:
+.. _execution profiling:
 
 Execution Profiling
 ===================
 
-For performance optimization, it is helpful to see statistics and visualize how
+For performance optimization, it is helpful to see statistics and visualize
-execution time is distributed in a verilated model.
+how execution time is distributed in a verilated model.
 
 With the :vlopt:`--prof-exec` option, Verilator will:
 
@@ -414,16 +411,19 @@ saved profiling file into a visual format and produce related statistics.
 
    Example verilator_gantt output, as viewed with GTKWave.
 
-   The measured_parallelism shows the number of CPUs being used at a given moment.
+   The measured_parallelism shows the number of CPUs being used at a given
+   moment.
 
-   The cpu_thread section shows which thread is executing on each physical CPU.
+   The cpu_thread section shows which thread is executing on each physical
+   CPU.
 
-   The thread_mtask section shows which macro-task is running on a given thread.
+   The thread_mtask section shows which macro-task is running on a given
+   thread.
 
 For more information, see :command:`verilator_gantt`.
 
 
-.. _Profiling ccache efficiency:
+.. _profiling ccache efficiency:
 
 Profiling ccache efficiency
 ===========================
@@ -431,8 +431,7 @@ Profiling ccache efficiency
 The Verilator-generated Makefile supports basic profiling of ccache
 behavior during the build. This can be used to track down files that might
 be unnecessarily rebuilt, though as of today, even minor code changes will
-usually require rebuilding a large number of files. Improving ccache
+usually require rebuilding a large number of files.
-efficiency during the edit/compile/test loop is an active development area.
 
 To get a basic report of how well ccache is doing, add the `ccache-report`
 target when invoking the generated Makefile:
@@ -445,13 +444,15 @@ This will print a report based on all executions of ccache during this
 invocation of Make. The report is also written to a file, in this example
 `obj_dir/Vout__cache_report.txt`.
 
-To use the `ccache-report` target, at least one other explicit build target
+To use the `ccache-report` target, OBJCACHE must be set to 'ccache' (this
-must be specified, and OBJCACHE must be set to 'ccache'.
+is done by `configure` if 'ccache' is installed). If no other explicit
+build targets are specified, `cchache-report` will build the `default`
+target.
 
 This feature is currently experimental and might change in subsequent
 releases.
 
-.. _Save/Restore:
+.. _save/restore:
 
 Save/Restore
 ============
@@ -464,8 +465,8 @@ what language features are supported along with :vlopt:`--savable`; if you
 attempt to use an unsupported feature, Verilator will throw an error.
 
 To use save/restore, the user wrapper code must create a VerilatedSerialize
-or VerilatedDeserialze object and then call the :code:`<<` or :code:`>>`
+or VerilatedDeserialze object and then call the ``<<`` or ``>>`` operators
-operators on the generated model and any other data the process needs to be
+on the generated model and any other data the process needs to be
 saved/restored. These functions are not thread-safe and are typically
 called only by a main thread.
 
@@ -495,8 +496,8 @@ collected by running your simulation executable; then this information is
 used to guide the next Verilation or compilation.
 
 There are two forms of profile-guided optimizations. Unfortunately, for
-best results, they must each be performed from the highest level code to the
+best results, they must each be performed from the highest level code to
-lowest, which means performing them separately and in this order:
+the lowest, which means performing them separately and in this order:
 
 * :ref:`Thread PGO`
 * :ref:`Compiler PGO`
@@ -506,13 +507,13 @@ toggle rate PGO, branch prediction PGO, statement execution time PGO, or
 others, as they prove beneficial.
 
 
-.. _Thread PGO:
+.. _thread pgo:
 
 Thread Profile-Guided Optimization
 ----------------------------------
 
-Verilator supports profile-guided optimization (Verilation) of multithreaded
+Verilator supports profile-guided optimization (Verilation) of
-models (Thread PGO) to improve performance.
+multithreaded models (Thread PGO) to improve performance.
 
 When using multithreading, Verilator computes how long macro tasks take and
 tries to balance those across threads. (What is a macro-task? See the
@@ -522,9 +523,9 @@ balanced, leading to decreased performance.  Thread PGO allows collecting
 profiling data to replace the estimates and better optimize these
 decisions.
 
-To use Thread PGO, Verilate the model with the :vlopt:`--prof-pgo` option. This
+To use Thread PGO, Verilate the model with the :vlopt:`--prof-pgo` option.
-will code to the verilated model to save profiling data for profile-guided
+This will code to the verilated model to save profiling data for
-optimization.
+profile-guided optimization.
 
 Run the model executable. When the executable exits, it will create a
 profile.vlt file.
@@ -543,8 +544,8 @@ Verilator.  Verilator will sum the profile results, so a long-running test
 will have more weight for optimization proportionally than a
 shorter-running test.
 
-If you provide any profile feedback data to Verilator and it cannot use
+If you provide any profile feedback data to Verilator and it cannot use it,
-it, it will issue the :option:`PROFOUTOFDATE` warning that threads were
+it will issue the :option:`PROFOUTOFDATE` warning that threads were
 scheduled using estimated costs. This usually indicates that the profile
 data was generated from a different Verilog source code than Verilator is
 currently running against. Therefore, repeat the data collection phase to
@@ -552,7 +553,7 @@ create new profiling data, then rerun Verilator with the same input source
 files and that new profiling data.
 
 
-.. _Compiler PGO:
+.. _compiler pgo:
 
 Compiler Profile-Guided Optimization
 ------------------------------------
@@ -573,8 +574,8 @@ Clang.  The process in GCC 10 was as follows:
       verilator [whatever_flags] --make \
           -CFLAGS -fprofile-generate -LDFLAGS -fprofile-generate
 
-   Or, if calling make yourself, add -fprofile-generate appropriately to your
+   Or, if calling make yourself, add -fprofile-generate appropriately to
-   Makefile.
+   your Makefile.
 
 2. Run your simulation. This will create \*.gcda file(s) in the same
    directory as the source files.
@@ -601,19 +602,18 @@ Clang.  The process in GCC 10 was as follows:
    your Makefile.
 
 Clang and GCC also support -fauto-profile, which uses sample-based
-feedback-directed optimization.  See the appropriate compiler
+feedback-directed optimization. See the appropriate compiler documentation.
-documentation.
 
 
-.. _Runtime Debugging:
+.. _runtime debugging:
 
 Runtime Debugging
 =================
 
 To debug a Verilated executable, Verilate with :vlopt:`--runtime-debug`.
 This will instruct the compiler to insert debugger, and enable various
-library assertions. These options slow down the executable, so do this
+library assertions. These options slow down the executable, so do this only
-only when debugging.
+when debugging.
 
 If you are using your own Makefiles, adapt appropriately to pass the
 options documented under :vlopt:`--runtime-debug` to the compiler and
@@ -622,7 +622,7 @@ linker.
 Once you have a debugging-enabled executable, run it using the the standard
 GNU debugger ``gdb`` or a similar tool, and create a backtrace; e.g.:
 
-   .. code-block:: bash
+.. code-block:: bash
 
    gdb obj_dir/Vtop
      run {Vtop_command_arguments}
@@ -635,5 +635,5 @@ find the maximum subset that still shows the issue.  E.g. it is likely that
 using `-CFLAGS -D_GLIBCXX_DEBUG` will not hide any bug, so may be used.
 
 Using :vlopt:`--runtime-debug` or `-CFLAGS -DVL_DEBUG=1` will only print a
-message if something goes wrong.  To enable debug print messages at
+message if something goes wrong. To enable debug print messages at runtime,
-runtime, additionally use the :vlopt:`+verilator+debug` runtime option.
+additionally use the :vlopt:`+verilator+debug` runtime option.

docs/guide/verilating.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 **********
@@ -22,12 +22,12 @@ Verilator may be used in five major ways:
   that may be used to feed into other user-designed tools.
 
 * With the :vlopt:`-E` option, Verilator will preprocess the code according
-  to IEEE preprocessing rules and write the output to standard out. This
+  to IEEE preprocessing rules and write the output to standard out. This is
-  is useful to feed other tools and to debug how "\`define" statements are
+  useful to feed other tools and to debug how "\`define" statements are
   expanded.
 
 
-.. _Binary, C++ and SystemC Generation:
+.. _binary, c++ and systemc generation:
 
 Binary, C++ and SystemC Generation
 ==================================
@@ -39,11 +39,11 @@ will translate into C++ and compile it into an executable binary with the
 
 When using these options:
 
-#. Verilator reads the input Verilog code and determines all "top modules", that
+#. Verilator reads the input Verilog code and determines all "top modules",
-   is, modules or programs that are not used as instances under other cells.
+   that is, modules or programs that are not used as instances under other
-   If :vlopt:`--top-module` is used, then that determines the top module, and
+   cells. If :vlopt:`--top-module` is used, then that determines the top
-   all other top modules are removed; otherwise a :vlopt:`MULTITOP` warning
+   module, and all other top modules are removed; otherwise a
-   is given.
+   :vlopt:`MULTITOP` warning is given.
 
 #. Verilator writes the C++/SystemC code to output files into the
    :vlopt:`--Mdir` option-specified directory, or defaults to "obj_dir".
@@ -65,7 +65,7 @@ Once a model is built, the next step is typically for the user to run it,
 see :ref:`Simulating`.
 
 
-.. _Finding and Binding Modules:
+.. _finding and binding modules:
 
 Finding and Binding Modules
 ===========================
@@ -74,13 +74,15 @@ Verilator provides several mechanisms to find the source code containing a
 module, primitive, interface, or program ("module" in this section) and
 bind them to an instantiation. These capabilities are similar to the
 "Precompiling in a single-pass" use model described in IEEE 1800-2023
-33.5.1, although `config` is not yet supported.
+33.5.1.
 
 Verilator first reads all files provided on the command line and
 :vlopt:`-f` files, and parses all modules within. Each module is assigned
 to the most recent library specified with :vlopt:`-work`, thus `-work liba
 a.v -work libb b.v` will assign modules in `a.v` to `liba` and modules in
-`b.v` to `libb`.
+`b.v` to `libb`. In the absence of a `-work` mapping, each module is
+optionally assigned to a library based on mappings provided by
+:vlopt:`-libmap`.
 
 If a module is not defined from a file on the command-line, Verilator
 attempts to find a filename constructed from the module name using
@@ -91,27 +93,27 @@ Verilator attempts to figure out the top module itself, and if multiple
 tops result a :option:`MULTITOP` warning is issued which may be suppressed
 (see details in :option:`MULTITOP`).
 
-Verilator will attempt to bind lower unresolved instances first in the same
+Verilator will attempt to bind lower unresolved instances based first on
-library name as the parent's instantiation library, and if not found search
+IEEE `config` specifications, second based on using the same library name
-globally across all libraries in the order modules were declared.  This
+as the parent's instantiation library, and finally search globally across
-allows otherwise conflicting duplicate module names between libraries to
+all libraries in the order modules were declared. This allows otherwise
-coexist uniquely within each library name.  When IEEE `config use` is
+conflicting duplicate module names between libraries to coexist uniquely
-supported, more complicated selections will be able to be specified.
+within each library name.
 
 
-.. _Hierarchical Verilation:
+.. _hierarchical verilation:
 
 Hierarchical Verilation
 =======================
 
 Large designs may take long (e.g., 10+ minutes) and huge memory (e.g., 100+
-GB) to Verilate.  In hierarchical mode, the user manually selects some
+GB) to Verilate. In hierarchical mode, the user manually selects some large
-large lower-level hierarchy blocks to separate from the larger design. For
+lower-level hierarchy blocks to separate from the larger design. For
 example, a core may be the hierarchy block separated out of a multi-core
 SoC design.
 
-Verilator is run in hierarchical mode on the whole SoC.  Verilator will
+Verilator is run in hierarchical mode on the whole SoC. Verilator will make
-make two models, one for the CPU hierarchy block and one for the SoC.  The
+two models, one for the CPU hierarchy block and one for the SoC. The
 Verilated code for the SoC will automatically call the CPU Verilated model.
 
 The current hierarchical Verilation is based on :vlopt:`--lib-create`. Each
@@ -165,18 +167,18 @@ But, the following usage is supported:
   hierarchy blocks.
 
 * Parameterized hierarchy block. Parameters of a hierarchy block can be
-  overridden using :code:`#(.param_name(value))` construct.
+  overridden using ``#(.param_name(value))`` construct.
 
 
-.. _Overlapping Verilation and Compilation:
+.. _overlapping verilation and compilation:
 
 Overlapping Verilation and Compilation
 --------------------------------------
 
 Verilator needs to run 2 + *N* times in hierarchical Verilation, where *N*
 is the number of hierarchy blocks. One of the two is for the top module,
-which refers to the wrappers of all other hierarchy blocks.  The second of the
+which refers to the wrappers of all other hierarchy blocks. The second of
-two is the initial run that searches modules marked with
+the two is the initial run that searches modules marked with
 :option:`/*verilator&32;hier_block*/` metacomment and creates a plan and
 write in :file:`{prefix}_hier.mk`. This initial run internally invokes
 other *N* + 1 runs, so you don't have to care about these *N* + 1 times of
@@ -194,16 +196,16 @@ Cross Compilation
 =================
 
 Verilator supports cross-compiling Verilated code. This is generally used
-to run Verilator on a Linux system and produce C++ code that is then compiled
+to run Verilator on a Linux system and produce C++ code that is then
-on Windows.
+compiled on Windows.
 
 Cross-compilation involves up to three different OSes. The build system is
 where you configure and compile Verilator, the host system is where you run
 Verilator, and the target system is where you compile the Verilated code
 and run the simulation.
 
-Verilator requires the build and host system types to be the
+Verilator requires the build and host system types to be the same, though
-same, though the target system type may be different.  To support this,
+the target system type may be different. To support this,
 :command:`./configure` and make Verilator on the build system. Then, run
 Verilator on the host system. Finally, the output of Verilator may be
 compiled on the different target system.
@@ -220,7 +222,7 @@ Makefiles produced by Verilator presume the target system is the same type
 as the build system.
 
 
-.. _Multithreading:
+.. _multithreading:
 
 Multithreading
 ==============
@@ -243,7 +245,7 @@ however, you can expect performance to be far worse than it would be with
 the proper ratio of threads and CPU cores.
 
 The thread used for constructing a model must be the same thread that calls
-:code:`eval()` into the model; this is called the "eval thread". The thread
+``eval()`` into the model; this is called the "eval thread". The thread
 used to perform certain global operations, such as saving and tracing, must
 be done by a "main thread". In most cases, the eval thread and main thread
 are the same thread (i.e. the user's top C++ testbench runs on a single
@@ -257,12 +259,13 @@ time of DPI imports.
 
 When using :vlopt:`--trace-vcd` to perform VCD tracing, the VCD trace
 construction is parallelized using the same number of threads as specified
-with :vlopt:`--threads`, and is executed on the same thread pool as the model.
+with :vlopt:`--threads`, and is executed on the same thread pool as the
+model.
 
 The :vlopt:`--trace-threads` options can be used with :vlopt:`--trace-fst`
-to offload FST tracing using multiple threads. If :vlopt:`--trace-threads` is
+to offload FST tracing using multiple threads. If :vlopt:`--trace-threads`
-given without :vlopt:`--threads`, then :vlopt:`--trace-threads` will imply
+is given without :vlopt:`--threads`, then :vlopt:`--trace-threads` will
-:vlopt:`--threads 1 <--threads>`, i.e., the support libraries will be
+imply :vlopt:`--threads 1 <--threads>`, i.e., the support libraries will be
 thread safe.
 
 With :vlopt:`--trace-threads 0 <--trace-threads>`, trace dumps are produced
@@ -271,8 +274,8 @@ on the main thread. This again gives the highest single-thread performance.
 With :vlopt:`--trace-threads {N} <--trace-threads>`, where N is at least 1,
 up to N additional threads will be created and managed by the trace files
 (e.g., VerilatedFstC), to offload construction of the trace dump. The main
-thread will be released to proceed with execution as soon as possible, though
+thread will be released to proceed with execution as soon as possible,
-some main thread blocking is still necessary while capturing the
+though some main thread blocking is still necessary while capturing the
 trace. FST tracing can utilize up to 2 offload threads, so there is no use
 of setting :vlopt:`--trace-threads` higher than 2 at the moment.
 
@@ -286,17 +289,17 @@ For best performance, use the :command:`numactl` program to (when the
 threading count fits) select unique physical cores on the same socket. The
 same applies for :vlopt:`--trace-threads` as well.
 
-As an example, if a model was Verilated with
+As an example, if a model was Verilated with :vlopt:`--threads 4
-:vlopt:`--threads 4 <--threads>`, we consult:
+<--threads>`, we consult:
 
 .. code-block:: bash
 
    egrep 'processor|physical id|core id' /proc/cpuinfo
 
 To select cores 0, 1, 2, and 3 that are all located on the same socket (0)
-but have different physical cores.  (Also useful is
+but have different physical cores. (Also useful is :command:`numactl
-:command:`numactl --hardware`, or :command:`lscpu`, but those don't show
+--hardware`, or :command:`lscpu`, but those don't show hyperthreading
-hyperthreading cores.)  Then we execute:
+cores.) Then we execute:
 
 .. code-block:: bash
 
@@ -305,15 +308,15 @@ hyperthreading cores.)  Then we execute:
 This will limit memory to socket 0, and threads to cores 0, 1, 2, 3,
 (presumably on socket 0), optimizing performance. Of course, this must be
 adjusted if you want another simulator to use, e.g., socket 1, or if you
-Verilated with a different number of threads.  To see what CPUs are
+Verilated with a different number of threads. To see what CPUs are actually
-actually used, use :vlopt:`--prof-exec`.
+used, use :vlopt:`--prof-exec`.
 
 
 Multithreaded Verilog and Library Support
 -----------------------------------------
 
-$display/$stop/$finish are delayed until the end of an eval() call
+$display/$stop/$finish are delayed until the end of an eval() call to
-to maintain ordering between threads. This may result in additional tasks
+maintain ordering between threads. This may result in additional tasks
 completing after the $stop or $finish.
 
 If using :vlopt:`--coverage`, the coverage routines are fully thread-safe.
@@ -335,7 +338,7 @@ IEEE to be multithreaded, Verilator requires all VPI calls are only made
 from the main thread.
 
 
-.. _GNU Make:
+.. _gnu make:
 
 GNU Make
 ========
@@ -347,7 +350,7 @@ If calling Verilator from a makefile, the :vlopt:`--MMD` option will create
 a dependency file, allowing Make to only run Verilator if input Verilog
 files change.
 
-.. _CMake:
+.. _cmake:
 
 CMake
 =====
@@ -364,8 +367,8 @@ would build the code listed in :ref:`Example C++ Execution`
    add_executable(Vour sim_main.cpp)
    verilate(Vour SOURCES our.v)
 
-:code:`find_package` will automatically find an installed copy of
+``find_package`` will automatically find an installed copy of Verilator, or
-Verilator, or use a local build if VERILATOR_ROOT is set.
+use a local build if VERILATOR_ROOT is set.
 
 Using CMake >= 3.12 and the Ninja generator is recommended, though other
 combinations should work. To build with CMake, change to the folder
@@ -393,10 +396,10 @@ If you're building the example, you should have an executable to run:
 
    ./Vour
 
-The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT,
+The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT, and
-and VERILATOR_BIN to the appropriate values and creates a verilate()
+VERILATOR_BIN to the appropriate values and creates a verilate() function.
-function. verilate() will automatically create custom commands to run
+verilate() will automatically create custom commands to run Verilator and
-Verilator and add the generated C++ sources to the target specified.
+add the generated C++ sources to the target specified.
 
 Verilate in CMake
 -----------------
@@ -417,8 +420,8 @@ if optional.
 verilate(target ...) can be called multiple times to add other Verilog
 modules to an executable or library target.
 
-When generating Verilated SystemC sources, you should list the
+When generating Verilated SystemC sources, you should list the SystemC
-SystemC include directories and link to the SystemC libraries.
+include directories and link to the SystemC libraries.
 
 .. describe:: target
 
@@ -547,7 +550,7 @@ The search paths can be configured by setting some variables:
    SYSTEMC_ROOT).
 
 
-.. _Verilation Summary Report:
+.. _verilation summary report:
 
 Verilation Summary Report
 =========================

docs/guide/warnings.rst

@@ -1,11 +1,11 @@
-.. Copyright 2003-2025 by Wilson Snyder.
+.. Copyright 2003-2026 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-=====================
+===================
- Errors and Warnings
+Errors and Warnings
-=====================
+===================
 
-.. _Disabling Warnings:
+.. _disabling warnings:
 
 Disabling Warnings
 ==================
@@ -13,7 +13,7 @@ Disabling Warnings
 Warnings may be disabled in multiple ways:
 
 #. Disable the warning globally by invoking Verilator with the
-   :code:`-Wno-{warning-code}` option.
+   ``-Wno-{warning-code}`` option.
 
    Global disables should be avoided, as they removes all checking across
    the source files, and prevents other users from compiling the sources
@@ -22,8 +22,8 @@ Warnings may be disabled in multiple ways:
 
 #. Disable the warning in the design source code. When the warning is
    printed, it will include a warning code. Surround the offending line
-   with a :code:`/*verilator&32;lint_off*/` and
+   with a ``/*verilator&32;lint_off*/`` and ``/*verilator&32;lint_on*/``
-   :code:`/*verilator&32;lint_on*/` metacomment pair:
+   metacomment pair:
 
    .. code-block:: sv
 
@@ -31,7 +31,6 @@ Warnings may be disabled in multiple ways:
       if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop;
       // verilator lint_on UNSIGNED
 
-
    A lint_off in the design source code will propagate down to any child
    files (files later included by the file with the lint_off), but will not
    propagate upwards to any parent file (file that included the file with
@@ -46,6 +45,9 @@ Warnings may be disabled in multiple ways:
 
       lint_off -rule UNSIGNED -file "*/example.v" -lines 1
 
+Metacomments and control file directives do not interact. If a warning is
+disabled by either metacomments, or a directive in a control file, it will
+not be emitted.
 
 Error And Warning Format
 ========================
@@ -57,11 +59,11 @@ expression:
 
    %(Error|Warning)(-[A-Z0-9_]+)?: ((\S+):(\d+):((\d+):)? )?.*
 
-
 Errors and warnings start with a percent sign (historical heritage from
 Digital Equipment Corporation). Some errors or warnings have a code
 attached, with meanings described below. Some errors also have a filename,
-line number, and optional column number (starting at column 1 to match GCC).
+line number, and optional column number (starting at column 1 to match
+GCC).
 
 Following the error message, Verilator will typically show the user's
 source code corresponding to the error, prefixed by the line number and a "
@@ -96,9 +98,9 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that an :code:`always_comb` block has a variable that is set
+   Warns that an ``always_comb`` block has a variable that is set after it
-   after it is used.  This may cause simulation-synthesis mismatches, as
+   is used. This may cause simulation-synthesis mismatches, as not all
-   not all simulators allow this ordering.
+   simulators allow this ordering.
 
    .. code-block:: sv
 
@@ -136,10 +138,10 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that a packed vector is declared with ascending bit range
+   Warns that a packed vector is declared with ascending bit range (i.e.
-   (i.e. [0:7]).  Descending bit range is now the overwhelming standard,
+   [0:7]). Descending bit range is now the overwhelming standard, and
-   and ascending ranges are now thus often due to simple oversight
+   ascending ranges are now thus often due to simple oversight instead of
-   instead of intent (a notable exception is the OpenPOWER code base).
+   intent (a notable exception is the OpenPOWER code base).
 
    It also warns that an instance is declared with ascending range
    (i.e. [0:7] or [7]) and is connected to an N-wide signal.
@@ -250,8 +252,8 @@ List Of Warnings
    warning may make Verilator simulations differ from other simulators.
 
    It is generally safe to disable this error (with a
-   :code:`// verilator lint_off BLKANDNBLK` metacomment or the
+   ``// verilator lint_off BLKANDNBLK`` metacomment or the
-   :code:`-Wno-BLKANDNBLK` option) when one of the assignments is inside a
+   ``-Wno-BLKANDNBLK`` option) when one of the assignments is inside a
    public task, or when the blocking and non-blocking assignments have
    non-overlapping bits and structure members.
 
@@ -323,8 +325,8 @@ List Of Warnings
 
    This message is only seen on large or complicated loops because
    Verilator generally unrolls small loops. You may want to try increasing
-   :vlopt:`--unroll-count` (and occasionally :vlopt:`--unroll-stmts`), which
+   :vlopt:`--unroll-count` (and occasionally :vlopt:`--unroll-stmts`),
-   will raise the small loop bar to avoid this error.
+   which will raise the small loop bar to avoid this error.
 
 
 .. option:: BLKSEQ
@@ -370,9 +372,9 @@ List Of Warnings
 
    Warns that inside a case statement, there is a stimulus pattern for
    which no case item is provided. This is bad style; if a case is
-   impossible, it's better to have a :code:`default: $stop;` or just
+   impossible, it's better to have a ``default: $stop;`` or just ``default:
-   :code:`default: ;` so that any design assumption violations will be
+   ;`` so that any design assumption violations will be discovered in the
-   discovered in the simulation.
+   simulation.
 
    Unique case statements that select on an enumerated variable, where all
    of the enumerated values are covered by case items, are considered
@@ -402,9 +404,10 @@ List Of Warnings
    .. TODO better example
 
    Warns that a case statement contains a constant with an ``x`` .
-   Verilator is two-state so interpret such items as always false.  Note that a
+   Verilator is two-state so interpret such items as always false. Note
-   frequent error is to use a ``X`` in a case or casez statement item; often,
+   that a frequent error is to use a ``X`` in a case or casez statement
-   what the user instead intended is to use a casez with ``?`` .
+   item; often, what the user instead intended is to use a casez with ``?``
+   .
 
    Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
@@ -414,8 +417,8 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that it is better style to use casez, and "?" in place of
+   Warns that it is better style to use casez, and "?" in place of "x"'s.
-   "x"'s.  See
+   See
    `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf
    <http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf>`_
 
@@ -427,13 +430,13 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that a dynamic cast ($cast) is unnecessary as the $cast will
+   Warns that a dynamic cast ($cast) is unnecessary as the ``$cast`` will
    always succeed or fail. If it will always fail, the $cast is useless,
    and if it will always succeed, a static cast may be preferred.
 
    Ignoring this warning will only suppress the lint check; it will
-   simulate correctly.  On other simulators, not fixing CASTCONST may
+   simulate correctly. On other simulators, not fixing CASTCONST may result
-   result in decreased performance.
+   in decreased performance.
 
 
 .. option:: CDCRSTLOGIC
@@ -464,8 +467,8 @@ List Of Warnings
    .. TODO better example
 
    Warns that the code is comparing a value in a way that will always be
-   constant.  For example, :code:`X > 1` will always be true when X is a
+   constant. For example, ``X > 1`` will always be true when X is a single
-   single bit wide.
+   bit wide.
 
    Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
@@ -473,9 +476,9 @@ List Of Warnings
 
 .. option:: COLONPLUS
 
-   Warns that a :code:`:+` is seen. Likely the intent was to use :code:`+:`
+   Warns that a ``:+`` is seen. Likely the intent was to use ``+:``
    to select a range of bits. If the intent was an explicitly positive
-   range, suggest adding a space, e.g., use :code:`: +`.
+   range, suggest adding a space, e.g., use ``: +``.
 
    Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
@@ -486,9 +489,9 @@ List Of Warnings
    .. TODO better example
 
    Warns that there is a delayed assignment inside of a combinatorial
-   block.  Using delayed assignments in this way is considered bad form,
+   block. Using delayed assignments in this way is considered bad form, and
-   and may lead to the simulator not matching synthesis.  If this message
+   may lead to the simulator not matching synthesis. If this message is
-   is suppressed, Verilator, like synthesis, will convert this to a
+   suppressed, Verilator, like synthesis, will convert this to a
    non-delayed assignment, which may result in logic races or other
    nasties. See
    `http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf
@@ -501,7 +504,7 @@ List Of Warnings
 .. option:: CONSTRAINTIGN
 
    Warns that Verilator does not support certain forms of
-   :code:`constraint`, :code:`constraint_mode`, or :code:`rand_mode`, and
+   ``constraint``, ``constraint_mode``, or ``rand_mode``, and
    the construct was ignored.
 
    Ignoring this warning may make Verilator randomize() simulations differ
@@ -510,13 +513,13 @@ List Of Warnings
 
 .. option:: CONSTWRITTEN
 
-   Error that a :code:`const` data typed variable is being assigned a
+   Error that a ``const`` data typed variable is being assigned a
    value.
 
    IEEE 1800-2023 6.20.6 requires this error.
 
    Suppressing this error will suppress the error message check; it will
-   simulate as if the :code:`const` as not present.
+   simulate as if the ``const`` as not present.
 
 
 .. option:: CONTASSREG
@@ -540,7 +543,7 @@ List Of Warnings
 .. option:: COVERIGN
 
    Warns that Verilator does not support certain forms of
-   :code:`covergroup`, :code:`coverpoint`, and coverage options, and the
+   ``covergroup``, ``coverpoint``, and coverage options, and the
    construct was ignored.
 
    Disabling the :option:`UNSUPPORTED` error also disables this warning.
@@ -554,11 +557,11 @@ List Of Warnings
    .. TODO better example
 
    Warns that a module or other declaration's name doesn't match the
-   filename with the path and extension stripped that it is declared in.  The
+   filename with the path and extension stripped that it is declared in.
-   filename a module/interface/program is declared in should match the
+   The filename a module/interface/program is declared in should match the
    name of the module etc., so that :vlopt:`-y` option directory searching
-   will work.  This warning is printed for only the first mismatching
+   will work. This warning is printed for only the first mismatching module
-   module in any given file, and :vlopt:`-v` library files are ignored.
+   in any given file, and :vlopt:`-v` library files are ignored.
 
    Disabled by default as this is a code-style warning; it will simulate
    correctly.
@@ -569,7 +572,7 @@ List Of Warnings
    Warns that a macro definition within the code is being overridden by a
    command line directive:
 
-   For example, running Verilator with :code:`<+define+\<DUP\>=\<def2\>>` and
+   For example, running Verilator with ``<+define+\<DUP\>=\<def2\>>`` and
 
    .. code-block:: sv
       :linenos:
@@ -592,8 +595,8 @@ List Of Warnings
 
 .. option:: DEFPARAM
 
-   Warns that the :code:`defparam` statement was deprecated in IEEE 1364-2001,
+   Warns that the ``defparam`` statement was deprecated in IEEE 1364-2001,
-   and all designs should now be using the :code:`#(...)` format to specify
+   and all designs should now be using the ``#(...)`` format to specify
    parameters.
 
    Defparams may be defined far from the instantiation affected by
@@ -625,7 +628,7 @@ List Of Warnings
       %Warning-DEFPARAM: example.v:5:15: defparam is deprecated (IEEE 1800-2023 C.4.1)
                                        : ... Suggest use instantiation with #(.MY_PARAM(...etc...))
 
-   To repair use :code:`#(.PARAMETER(...))` syntax. Repaired Example:
+   To repair use ``#(.PARAMETER(...))`` syntax. Repaired Example:
 
    .. code-block:: sv
       :linenos:
@@ -682,24 +685,23 @@ List Of Warnings
    passing. Thus to prevent an infinite loop, the Verilated executable
    gives the DIDNOTCONVERGE error.
 
-   To debug this, first, review any UNOPTFLAT warnings that were
+   To debug this, first, review any UNOPTFLAT warnings that were ignored.
-   ignored.  Though typically, it is safe to ignore UNOPTFLAT (at a
+   Though typically, it is safe to ignore UNOPTFLAT (at a performance
-   performance cost), at the time of issuing a UNOPTFLAT Verilator did not
+   cost), at the time of issuing a UNOPTFLAT Verilator did not know if the
-   know if the logic would eventually converge and assumed it would.
+   logic would eventually converge and assumed it would.
 
-   Next, run Verilator with
+   Next, run Verilator with :vlopt:`--prof-cfuncs -CFLAGS -DVL_DEBUG
-   :vlopt:`--prof-cfuncs -CFLAGS -DVL_DEBUG <--prof-cfuncs>`.  Rerun the
+   <--prof-cfuncs>`. Rerun the test. Now just before the convergence error,
-   test.  Now just before the convergence error, you should see additional
+   you should see additional output similar to this:
-   output similar to this:
 
    .. include:: ../../docs/gen/ex_DIDNOTCONVERGE_msg.rst
 
    The CHANGE line means that the signal 'a' kept changing on the given
    filename and line number that drove the signal. Inspect the code that
    modifies these signals. Note that if many signals are getting printed,
-   then most likely, all of them are oscillating.  It may also be that,
+   then most likely, all of them are oscillating. It may also be that, e.g.
-   e.g. "a" may be oscillating, then "a" feeds signal "c", which then is
+   "a" may be oscillating, then "a" feeds signal "c", which then is also
-   also reported as oscillating.
+   reported as oscillating.
 
    One way DIDNOTCONVERGE may occur is flops are built out of gate
    primitives. Verilator does not support building flops or latches out of
@@ -709,8 +711,8 @@ List Of Warnings
    Another way DIDNOTCONVERGE may occur is if # delays are used to generate
    clocks if Verilator is run with :vlopt:`--no-timing`. In this mode,
    Verilator ignores the delays and gives an :option:`ASSIGNDLY` or
-   :option:`STMTDLY` warning.  If these were suppressed, due to the absence of
+   :option:`STMTDLY` warning. If these were suppressed, due to the absence
-   the delay, the design might oscillate.
+   of the delay, the design might oscillate.
 
    Finally, rare, more difficult cases can be debugged like a C++ program;
    either enter :command:`gdb` and use its tracing facilities, or edit the
@@ -719,8 +721,8 @@ List Of Warnings
 
 .. option:: ENCAPSULATED
 
-   Warns that a class member is declared :code:`local` or
+   Warns that a class member is declared ``local`` or
-   :code:`protected`, but is being accessed from outside that class (if
+   ``protected``, but is being accessed from outside that class (if
    local) or a derived class (if protected).
 
    Ignoring this warning will only suppress the lint check; it will
@@ -788,9 +790,9 @@ List Of Warnings
 
 .. option:: ENUMVALUE
 
-   An error that an enum data type value is being assigned from another data
+   An error that an enum data type value is being assigned from another
-   type that is not implicitly assignment compatible with that enumerated
+   data type that is not implicitly assignment compatible with that
-   type.  IEEE requires this error, but it may be disabled.
+   enumerated type. IEEE requires this error, but it may be disabled.
 
    Faulty example:
 
@@ -894,7 +896,7 @@ List Of Warnings
       %Warning-GENUNNAMED: example.v:2:9: Unnamed generate block (IEEE 1800-2023 27.6)
 
    To fix this assign a label (often with the naming convention prefix of
-   :code:`gen_` or :code:`g_`), for example:
+   ``gen_`` or ``g_``), for example:
 
    .. code-block:: sv
       :linenos:
@@ -941,10 +943,9 @@ List Of Warnings
 
    Warns that if/if else statements have exceeded the depth specified with
    :vlopt:`--if-depth`, as they are likely to result in slow priority
-   encoders.  Statements below unique and priority :code:`if` statements
+   encoders. Statements below unique and priority ``if`` statements are
-   are ignored.  Solutions include changing the code to a case statement,
+   ignored. Solutions include changing the code to a case statement, or
-   or using a SystemVerilog :code:`unique if` or :code:`priority if`
+   using a SystemVerilog ``unique if`` or ``priority if`` statement.
-   statement.
 
    Disabled by default as this is a code-style warning; it will simulate
    correctly.
@@ -1003,11 +1004,11 @@ List Of Warnings
    .. TODO better example
 
    Warns that a wire is being implicitly declared (it is a single-bit wide
-   output from a sub-module.)  While legal in Verilog, implicit
+   output from a sub-module.) While legal in Verilog, implicit declarations
-   declarations only work for single-bit wide signals (not buses), do not
+   only work for single-bit wide signals (not buses), do not allow using a
-   allow using a signal before it is implicitly declared by an instance,
+   signal before it is implicitly declared by an instance, and can lead to
-   and can lead to dangling nets.  A better option is the
+   dangling nets. A better option is the ``/*AUTOWIRE*/`` feature of
-   :code:`/*AUTOWIRE*/` feature of Verilog-Mode for Emacs, available from
+   Verilog-Mode for Emacs, available from
    `https://www.veripool.org/verilog-mode
    <https://www.veripool.org/verilog-mode>`_
 
@@ -1046,10 +1047,10 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that an :code:`import {package}::*` statement is in $unit
+   Warns that an ``import {package}::*`` statement is in $unit
    scope. This causes the imported symbols to pollute the global namespace,
    defeating much of the purpose of having a package. Generally,
-   :code:`import ::*` should only be used inside a lower scope, such as a
+   ``import ::*`` should only be used inside a lower scope, such as a
    package or module.
 
    Disabled by default as this is a code-style warning; it will simulate
@@ -1076,9 +1077,8 @@ List Of Warnings
    Warns that an "\`include" filename specifies an absolute path. This
    means the code will not work on any other system with a different file
    system layout. Instead of using absolute paths, relative paths
-   (preferably without any directory specified) should be used,
+   (preferably without any directory specified) should be used, and +incdir
-   and +incdir used on the command line to specify the top include source
+   used on the command line to specify the top include source directories.
-   directories.
 
    Disabled by default as this is a code-style warning; it will simulate
    correctly.
@@ -1088,7 +1088,7 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that a :code:`while` or :code:`for` statement has a condition that
+   Warns that a ``while`` or ``for`` statement has a condition that
    is always true, and thus results in an infinite loop if the statement
    ever executes.
 
@@ -1104,9 +1104,9 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that the code has a delayed assignment inside of an :code:`initial`
+   Warns that the code has a delayed assignment inside of an ``initial`` or
-   or :code:`final` block.  If this message is suppressed, Verilator will
+   ``final`` block. If this message is suppressed, Verilator will convert
-   convert this to a non-delayed assignment.  See also :option:`COMBDLY`.
+   this to a non-delayed assignment. See also :option:`COMBDLY`.
 
    Ignoring this warning may make Verilator simulations differ from other
    simulators.
@@ -1254,13 +1254,13 @@ List Of Warnings
 .. option:: MISINDENT
 
    Warns that the indentation of a statement is misleading, suggesting the
-   statement is part of a previous :code:`if` or :code:`while` block while
+   statement is part of a previous ``if`` or ``while`` block while
    it is not.
 
    Verilator suppresses this check when there is an inconsistent mix of
    spaces and tabs, as it cannot ensure the width of tabs. Verilator also
-   ignores blocks with :code:`begin`/:code:`end`, as the :code:`end`
+   ignores blocks with ``begin``/``end``, as the ``end`` visually indicates
-   visually indicates the earlier statement's end.
+   the earlier statement's end.
 
    Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
@@ -1303,8 +1303,8 @@ List Of Warnings
    Warns that a module has multiple definitions. Generally, this indicates
    a coding error, or a mistake in a library file, and it's good practice
    to have one module per file (and only put each file once on the command
-   line) to avoid these issues.  For some gate level netlists duplicates
+   line) to avoid these issues. For some gate level netlists duplicates are
-   are sometimes unavoidable, and MODDUP should be disabled.
+   sometimes unavoidable, and MODDUP should be disabled.
 
    Ignoring this warning will cause the more recent module definition to be
    discarded.
@@ -1325,7 +1325,7 @@ List Of Warnings
 
 .. option:: MULTIDRIVEN
 
-   Warns that the specified signal comes from multiple :code:`always`
+   Warns that the specified signal comes from multiple ``always``
    blocks, each with different clocking. This warning does not look at
    individual bits (see the example below).
 
@@ -1407,8 +1407,8 @@ List Of Warnings
 .. option:: NOEFFECT
 
    Warns that the statement will have no effect and is roughly equivalent
-   to not being present.  This is only issued when it is "non-obvious",
+   to not being present. This is only issued when it is "non-obvious", e.g.
-   e.g. a :code:`if (0)` will not result in this warning.
+   a ``if (0)`` will not result in this warning.
 
    Faulty example:
 
@@ -1435,8 +1435,8 @@ List Of Warnings
 
    Warns when a non-standard language feature is used that has a standard
    equivalent, which might behave differently in corner cases. For example
-   :code:`$psprintf` system function is replaced by its standard equivalent
+   ``$psprintf`` system function is replaced by its standard equivalent
-   :code:`$sformatf`.
+   ``$sformatf``.
 
    Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
@@ -1455,9 +1455,9 @@ List Of Warnings
 
    .. include:: ../../docs/gen/ex_NORETURN_msg.rst
 
-   To fix the issue, add a :code:`return` statement, or set the output
+   To fix the issue, add a ``return`` statement, or set the output
    variable of the function, or make the function of data type
-   :code:`void`.
+   ``void``.
 
    Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
@@ -1520,10 +1520,10 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that an instance has a pin that is connected to
+   Warns that an instance has a pin that is connected to ``.pin_name()``,
-   :code:`.pin_name()`, e.g., not another signal, but with an explicit
+   e.g., not another signal, but with an explicit mention of the pin. It
-   mention of the pin.  It may be desirable to disable PINCONNECTEMPTY, as
+   may be desirable to disable PINCONNECTEMPTY, as this indicates the
-   this indicates the intention to have a no-connect.
+   intention to have a no-connect.
 
    Disabled by default as this is a code-style warning; it will simulate
    correctly.
@@ -1533,9 +1533,9 @@ List Of Warnings
 
    .. TODO better example (frequent)
 
-   Warns that a module has a pin that is not mentioned in an instance.  If
+   Warns that a module has a pin that is not mentioned in an instance. If a
-   a pin is not missing it should still be specified on the instance
+   pin is not missing it should still be specified on the instance
-   declaration with an empty connection using :code:`(.pin_name())`.
+   declaration with an empty connection using ``(.pin_name())``.
 
    Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
@@ -1639,10 +1639,10 @@ List Of Warnings
 .. option:: PREPROCZERO
 
    Warns that a preprocessor \`ifdef/\`ifndef expression (added in IEEE
-   1800-2023) evaluates a define value which has a value of :code:`0`.
+   1800-2023) evaluates a define value which has a value of ``0``.
-   This will evaluate in the expression as :code:`1` because the define has
+   This will evaluate in the expression as ``1`` because the define has
    a definition, unlike in the C preprocessor, which evaluates using the
-   define's value (of :code:`1`).
+   define's value (of ``1``).
 
    Referring to a define with an empty value does not give this warning, as
    in C, the preprocessor will give an error on a preprocessor expression
@@ -1708,9 +1708,9 @@ List Of Warnings
    Warns that threads were scheduled using estimated costs, even though
    that data was provided from profile-guided optimization (see
    :ref:`Thread PGO`) as fed into Verilator using the
-   :option:`profile_data` configuration file option.  This usually
+   :option:`profile_data` configuration file option. This usually indicates
-   indicates that the profile data was generated from a different Verilog
+   that the profile data was generated from a different Verilog source code
-   source code than Verilator is currently running against.
+   than Verilator is currently running against.
 
    It is recommended to create new profiling data, then rerun Verilator
    with the same input source files and that new profiling data.
@@ -1744,11 +1744,11 @@ List Of Warnings
 
 .. option:: RANDC
 
-   Historical, never issued since version 5.018, when :code:`randc` became
+   Historical, never issued since version 5.018, when ``randc`` became
    fully supported.
 
-   Warned that the :code:`randc` keyword was unsupported and was converted
+   Warned that the ``randc`` keyword was unsupported and was converted
-   to :code:`rand`.
+   to ``rand``.
 
 
 .. option:: REALCVT
@@ -1811,9 +1811,9 @@ List Of Warnings
                            example.v:1:20: ... Location of previous definition, with value: 'def2'
 
    The best solution is to use a different name for the second macro. If
-   this is infeasible, add an undef to indicate that the code overriding the
+   this is infeasible, add an undef to indicate that the code overriding
-   value. This will express the intent and should avoid future warnings on
+   the value. This will express the intent and should avoid future warnings
-   any linting tool:
+   on any linting tool:
 
    .. code-block:: sv
 
@@ -1873,27 +1873,25 @@ List Of Warnings
 
 .. option:: SHORTREAL
 
-   Warns that Verilator does not support :code:`shortreal`, and they will be
+   Warns that Verilator does not support ``shortreal``, and they will be
-   automatically promoted to :code:`real`.
+   automatically promoted to ``real``.
 
    .. code-block:: sv
       :linenos:
-      :emphasize-lines: 1
 
       shortreal sig;  //<--- Warning
 
-   The recommendation is to replace any :code:`shortreal` in the code with
+   The recommendation is to replace any ``shortreal`` in the code with
-   :code:`real`, as :code:`shortreal` is not widely supported across
+   ``real``, as ``shortreal`` is not widely supported across
    industry tools.
 
    .. code-block:: sv
       :linenos:
-      :emphasize-lines: 1
 
       real sig;  //<--- Repaired
 
    Ignoring this warning may make Verilator simulations differ from other
-   simulators if the increased precision of :code:`real` affects the
+   simulators if the increased precision of ``real`` affects the
    modeled values, or DPI calls.
 
 
@@ -1910,7 +1908,6 @@ List Of Warnings
 
    .. code-block:: sv
       :linenos:
-      :emphasize-lines: 1
 
       x = y[a++];
 
@@ -1933,7 +1930,7 @@ List Of Warnings
 .. option:: SPECIFYIGN
 
    Warns that Verilator does not support certain constructs in
-   :code:`specify` blocks, nor :code:`$sdf_annotate`, and the construct was
+   ``specify`` blocks, nor ``$sdf_annotate``, and the construct was
    ignored.
 
    Disabling the :option:`UNSUPPORTED` error also disables this warning.
@@ -1956,14 +1953,14 @@ List Of Warnings
    * The index of the array exceeds the array size.
 
    * The variable is accessed from outside using a dotted reference.
-     (e.g. :code:`top.instance0.variable0 = 1`).
+     (e.g. ``top.instance0.variable0 = 1``).
 
    * The variable is not declared in a module, but in a package or an
      interface.
 
    * The variable is a parameter, localparam, genvar, or queue.
 
-   * The variable is tristate or bidirectional. (e.g., :code:`inout`).
+   * The variable is tristate or bidirectional. (e.g., ``inout``).
 
 
 .. option:: STATICVAR
@@ -1992,11 +1989,11 @@ List Of Warnings
 
    .. include:: ../../docs/gen/ex_STMTDLY_msg.rst
 
-   This warning is issued only if Verilator is run with :vlopt:`--no-timing`.
+   This warning is issued only if Verilator is run with
-   All delays on statements are ignored in this mode.  In many cases ignoring a
+   :vlopt:`--no-timing`. All delays on statements are ignored in this mode.
-   delay might be harmless, but if the delayed statement is, as in this
+   In many cases ignoring a delay might be harmless, but if the delayed
-   example, used to cause some important action later, it might be an
+   statement is, as in this example, used to cause some important action
-   important difference.
+   later, it might be an important difference.
 
    Some possible workarounds:
 
@@ -2009,14 +2006,32 @@ List Of Warnings
    * Run Verilator with :vlopt:`--timing`.
 
 
+.. option:: SUPERNFIRST
+
+   An error that a `super.new` is not the first statement in a `function
+   new`.
+
+   IEEE requires this error. Ignoring this warning may cause other errors
+   or initialization ordering surprises, as described in IEEE 1800-2023
+   8.15.
+
+   Faulty example:
+
+   .. include:: ../../docs/gen/ex_SUPERNFIRST_faulty.rst
+
+   Results in:
+
+   .. include:: ../../docs/gen/ex_SUPERNFIRST_msg.rst
+
+
 .. option:: SYMRSVDWORD
 
    Warning that a symbol matches a C++ reserved word, and using this as a
    symbol name would result in odd C++ compiler errors. You may disable
-   this warning, but Verilator will rename the symbol to avoid conflict.
+   this warning, but Verilator will rename the symbol to avoid conflict. If
-   If you are using `--vpi` and only mark things as public for VPI access
+   you are using `--vpi` and only mark things as public for VPI access (and
-   (and not C++ access) then it is advisable to disable this warning with
+   not C++ access) then it is advisable to disable this warning with
-   :code:`-Wno-SYMRSVDWORD`.
+   ``-Wno-SYMRSVDWORD``.
 
 
 .. option:: SYNCASYNCNET
@@ -2168,7 +2183,7 @@ List Of Warnings
       wire [2:0] x = {x[1:0], shift_in};
 
    This statement needs to be evaluated multiple times, as a change in
-   :code:`shift_in` requires "x" to be computed three times before it becomes
+   ``shift_in`` requires "x" to be computed three times before it becomes
    stable. This is because a change in "x" requires "x" itself to change
    its value, which causes the warning.
 
@@ -2198,11 +2213,10 @@ List Of Warnings
 
    Occasionally UNOPTFLAT may be indicated when there is a true
    circulation. e.g., if trying to implement a flop or latch using
-   individual gate primitives.  If UNOPTFLAT is suppressed, the code may
+   individual gate primitives. If UNOPTFLAT is suppressed, the code may get
-   get a DIDNOTCONVERGE error. Verilator does not support building flops or
+   a DIDNOTCONVERGE error. Verilator does not support building flops or
    latches out of gate primitives, and any such code must change to use
-   behavioral constructs (e.g., :code:`always_ff` and
+   behavioral constructs (e.g., ``always_ff`` and ``always_latch``).
-   :code:`always_latch`).
 
    Another way to resolve this warning is to add a
    :option:`/*verilator&32;split_var*/` metacomment described above. This
@@ -2264,7 +2278,7 @@ List Of Warnings
    .. TODO better example
 
    Warns that the code is comparing an unsigned value in a way that implies
-   it is signed; for example :code:`X < 0` will always be false when X is
+   it is signed; for example ``X < 0`` will always be false when X is
    unsigned.
 
    Ignoring this warning will only suppress the lint check; it will
@@ -2287,6 +2301,8 @@ List Of Warnings
    make the design simulate incorrectly and is only intended for lint
    usage; see the details under :vlopt:`--bbox-unsup`.
 
+   Disabling this error also disables :option:`COVERIGN` and
+   :option:`SPECIFYIGN`.
 
 .. option:: UNUSED
 
@@ -2344,11 +2360,11 @@ List Of Warnings
                           sig_not_used_yet_b,  // To be fixed
                           1'b0};
 
-   The AND with constant zero mean the net will always be zero,
+   The AND with constant zero mean the net will always be zero, so won't
-   so won't use simulation runtime.  The redundant leading and trailing
+   use simulation runtime. The redundant leading and trailing zeros avoid
-   zeros avoid syntax errors if there are no signals between them.  The
+   syntax errors if there are no signals between them. The magic name
-   magic name "unused" (controlled by the :vlopt:`--unused-regexp` option)
+   "unused" (controlled by the :vlopt:`--unused-regexp` option) is
-   is recognized by Verilator and suppresses warnings; if using other lint
+   recognized by Verilator and suppresses warnings; if using other lint
    tools, either teach the tool to ignore signals with "unused" in the
    name, or put the appropriate lint_off around the wire. Having unused
    signals in one place makes it easy to find what is unused and reduces
@@ -2469,22 +2485,26 @@ List Of Warnings
    and will suppress the warning when the minimum width is appropriate to
    fit the required size.
 
-   Ignoring this warning will only suppress the lint check; it will
+   Disabling/enabling WIDTH is equivalent to disabling/enabling the
+   :option:`WIDTHEXPAND`, :option:`WIDTHTRUNC`, and :option:`WIDTHXZEXPAND`
+   warnings.
+
+   Ignoring these warnings will only suppress the lint check; it will
    simulate correctly.
 
    The recommendation is to fix these issues by:
 
    * Resize the variable or constant to match the needed size for the
-     expression.  E.g., :code:`2'd2` instead of :code:`3'd2`.
+     expression. E.g., ``2'd2`` instead of ``3'd2``.
 
-   * Using :code:`'0` or :code:`'1`, which automatically resize in an
+   * Using ``'0`` or ``'1``, which automatically resize in an
      expression.
 
-   * Using part selects to narrow a variable; e.g., :code:`too_wide[1:0]`.
+   * Using part selects to narrow a variable; e.g., ``too_wide[1:0]``.
 
-   * Using concatenate to widen a variable; e.g., :code:`{1'b1, too_narrow}`.
+   * Using concatenate to widen a variable; e.g., ``{1'b1, too_narrow}``.
 
-   * Using cast to resize a variable; e.g., :code:`23'(wrong_sized)`.
+   * Using cast to resize a variable; e.g., ``23'(wrong_sized)``.
 
    For example, this is a missized index:
 
@@ -2502,8 +2522,8 @@ List Of Warnings
 .. option:: WIDTHCONCAT
 
    Warns that based on the width rules of Verilog, a concatenate, or
-   replication has an indeterminate width.  In most cases, this violates
+   replication has an indeterminate width. In most cases, this violates the
-   the Verilog rule that widths inside concatenates and replicates must be
+   Verilog rule that widths inside concatenates and replicates must be
    sized and should be fixed in the code.
 
    Faulty example:
@@ -2519,9 +2539,9 @@ List Of Warnings
       parameter PAR = 1;
       wire [63:0] concat = {PAR, PAR};
 
-   The correct fix is to either size the 1 (:code:`32'h1`), add the
+   The correct fix is to either size the 1 (``32'h1``), add the
-   width to the parameter definition (:code:`parameter [31:0]`), or add the
+   width to the parameter definition (``parameter [31:0]``), or add the
-   width to the parameter usage (:code:`{PAR[31:0], PAR[31:0]}`).
+   width to the parameter usage (``{PAR[31:0], PAR[31:0]}``).
 
 
 .. option:: WIDTHEXPAND

docs/spelling.txt

@@ -1,11 +1,16 @@
 ABCp
 Aadi
 Accellera
+Aditya
 Affe
 Aleksander
 Alexandre
+Alkhatib
+Almis
+Amal
 Ami
 Amir
+Amirreza
 Anastasiadis
 Anglin
 Anikin
@@ -13,6 +18,7 @@ Antmicro
 Antonin
 Antwerpen
 Arasanipalai
+Araweelo
 Arjen
 Arshid
 Asciidoc
@@ -34,8 +40,10 @@ Biancolin
 Binderman
 Björk
 Bleiweiss
+Boden
 Bogdan
 Bonneau
+Borgne
 Bouchard
 Boumenot
 Brej
@@ -55,8 +63,10 @@ Cherkasov
 Chih
 Chitlesh
 Christophe
+Chusov
 Cochrane
 Conda
+Connor
 Corteggiani
 Cozzocrea
 Cuan
@@ -87,11 +97,13 @@ Dinotrace
 Djordjevic
 Dobbie
 Dockerfile
+Domenic
 Donal
 Donovick
 Doorn
 Doxygen
 Dressler
+Driscoll
 Dudek
 Duraid
 Dutton
@@ -105,6 +117,7 @@ Eiler
 Eivind
 El
 Elbourne
+Eldridge
 Elzeftawi
 Embecosm
 Engstrom
@@ -117,18 +130,22 @@ Faure
 Feinberg
 Fekete
 Ferrandi
+Fiergolski
 Filip
 Flachs
 Flavien
 Florian
 Foletto
+Fonarev
 Forencich
 Forker
+Fractile
 Francillon
 Fredieu
 Freiberger
 Frédéric
 GTKWave
+Gagnon
 Galbi
 Gantt
 Garnal
@@ -146,24 +163,30 @@ Gisselquist
 Gladkikh
 GmbH
 Goessling
+Goh
 Gonnen
 Goorah
 Gossner
+Goto
 Graba
 Graphviz
 Graybeal
 Grobman
 Grulfen
 Gu
+Gugala
 Gunter
 Guo
+Gustafsson
 Güzel
 Hameed
+Hammoud
 Hao
 Haojin
 Harboe
 Hashimoto
 Hayenga
+Heng
 Hesselbarth
 Hewson
 Hicamp
@@ -181,6 +204,7 @@ Hyperthreading
 Ibrahim
 Ikram
 Iles
+Ille
 Inlines
 Inout
 Iru
@@ -194,10 +218,14 @@ Jannis
 Jasen
 Jens
 Jeras
+Jha
+Jian
 Jiaxun
+Jitesh
 Jiuyang
 Joannou
 Joly
+Jongenburger
 Josse
 Jullien
 Junji
@@ -215,6 +243,8 @@ Karge
 Karlsson
 Katz
 Katzman
+Kazemi
+Kees
 Kelin
 Keren
 Keyi
@@ -234,6 +264,7 @@ Kouping
 Kravitz
 Krolnik
 Kruse
+Kubalek
 Kumashikar
 Kuoping
 Kurachi
@@ -255,6 +286,7 @@ Lockhart
 Longo
 LteS
 Luca
+Lueker
 Luiza
 Lussier
 Lübeck
@@ -268,6 +300,7 @@ Mahmoudy
 Makefile
 Makefiles
 Maksymenko
+Marche
 Markley
 Marquet
 Matveyenko
@@ -293,6 +326,7 @@ ModelSim
 Modport
 Moinak
 Mong
+Mora
 Muhlestein
 Multithreaded
 Multithreading
@@ -305,31 +339,40 @@ Narayan
 Narcis
 Nassim
 Nauticus
+Nayak
+Nenakhov
 Newgard
 Nigam
 Nikana
+Nikolay
 Niraj
 Niranjan
 Nitza
 Noack
 Nodine
+Nurczyński
 Ober
 Oleg
 Oler
 Olof
 Olofsson
+Ondrej
 Oron
 Oyvind
 PLI
 Palaniappan
 Patricio
+Peltonen
 Petr
+Petrisko
+Pham
 Piard
 Piechotka
 Piersall
 Platz
 Platzer
 Plunkett
+Poikela
 Popolon
 Popov
 Prabhat
@@ -345,16 +388,19 @@ Priyadharshini
 Pullup
 Pulver
 Puri
+Puzanov
 Qin
 Qiu
 Questa
 Rachit
 Ralf
+Ranjan
 Rapp
 Redhat
 Reitan
 Renga
 Requin
+Riaz
 Rodas
 Rodionov
 Rohan
@@ -362,10 +408,12 @@ Rolfe
 Rontionov
 Roodselaar
 Roshit
+Ruelas
 Rufer
 Runtime
 Ruud
 Rystsov
+Rémi
 STandarD
 Salman
 Sammelson
@@ -373,6 +421,7 @@ Sanggyu
 Sanguinetti
 Sanjay
 Sasselli
+Sauter
 Scharrer
 Schless
 Seitz
@@ -388,6 +437,7 @@ Shi
 Shinkarovsky
 Shinya
 Shirakawa
+Shivaram
 Shou
 Shuba
 Shunyao
@@ -437,12 +487,15 @@ Timi
 Tomov
 Tood
 Topa
+Toshiki
 Tota
 Trefor
 Tresidder
 Tri
 Tristate
 Truong
+Tung
+Tuomas
 Turton
 UNOPTFLAT
 Ubixum
@@ -451,6 +504,7 @@ Uints
 Undefine
 Undefines
 Unsized
+Uppal
 Urbach
 Uselib
 Usha
@@ -479,7 +533,9 @@ Vlip
 Vm
 Vukobratovic
 Wai
+Wajahat
 Wasson
+Weijie
 Welch
 Werror
 Wfuture
@@ -495,10 +551,12 @@ Wouters
 Wpedantic
 Wunused
 Wwarn
+Wüthrich
 XSim
 Xcelium
 Xiaoliang
 Xiaoyi
+Xie
 Xuan
 Xuanqi
 Yao
@@ -612,6 +670,7 @@ countbits
 countones
 cout
 covergroup
+covergroups
 cpp
 cppstyle
 cpu
@@ -619,6 +678,7 @@ cpure
 ctor
 ctrace
 cutable
+cxx
 cygwin
 dM
 da
@@ -713,6 +773,7 @@ expr
 extern
 ezchi
 fanin
+fargs
 fasttrace
 fauto
 fbranch
@@ -792,6 +853,7 @@ incdir
 includer
 incrementing
 inferfaces
+informationals
 inhibitSim
 initarray
 initializer
@@ -813,6 +875,7 @@ jobserver
 json
 jwoutersymatra
 killua
+kiow
 lang
 lcov
 ld
@@ -821,6 +884,7 @@ len
 libc
 libext
 libgoogle
+liblist
 libsystemc
 libtcmalloc
 libverilated
@@ -876,6 +940,7 @@ multipoint
 multithread
 multithreaded
 multithreading
+multitop
 musl
 mutex
 mutexes
@@ -976,6 +1041,8 @@ qrqiuren
 radix
 randc
 randcase
+randmode
+randsequence
 randstate
 raphmaster
 rarr
@@ -1138,6 +1205,7 @@ vcoverage
 vdhotre
 vec
 ventana
+venv
 ver
 verFiles
 verible
@@ -1150,6 +1218,7 @@ verimake
 veriuser
 vl
 vlSelf
+vla
 vlopt
 vlt
 vltstd
@@ -1161,6 +1230,7 @@ vpiInertialDelay
 vpiInstance
 vpiLeftRange
 vpiModule
+vpiSigned
 vpiSize
 vpiSuppressVal
 vpiTimeUnit

docs/xml.rst

@@ -29,22 +29,22 @@ Structure
 The XML document consists of 4 sections within the top level
 ``verilator_xml`` element:
 
-``<files>``\ ... ``</files>``
+``<files>``... ``</files>``
    This section contains a list of all design files read, including the
    built-in constructs and the command line as their own entries. Each
-   ``<file>`` has an attribute ``id`` which is a short ASCII string
+   ``<file>`` has an attribute ``id`` which is a short ASCII string unique
-   unique to that file. Other elements' ``loc`` attributes use this id
+   to that file. Other elements' ``loc`` attributes use this id to refer to
-   to refer to a particular file.
+   a particular file.
 
-``<module_files>``\ ... ``</module_files>``
+``<module_files>``... ``</module_files>``
    All files containing Verilog module definitions are listed in this
    section. This element's contents is a subset of the ``<files>``
    element's contents.
 
-``<cells>``\ ... ``</cells>``
+``<cells>``... ``</cells>``
    The cells section of the XML document contains the design instance
-   hierarchy. Each instance is represented with the ``<cell>`` element
+   hierarchy. Each instance is represented with the ``<cell>`` element with
-   with the following attributes:
+   the following attributes:
 
    - ``loc``: The file id, first line number, last line number, first
      column number and last column number of the identifier where the
@@ -52,25 +52,24 @@ The XML document consists of 4 sections within the top level
 
    - ``name``: The instance name.
 
-   -  ``submodname``: The module name uniquified with particular
+   - ``submodname``: The module name uniquified with particular parameter
-      parameter values (if any).
+     values (if any).
 
    - ``hier``: The full hierarchy path.
 
-``<netlist>``\ ... ``</netlist>``
+``<netlist>``... ``</netlist>``
-   The netlist section contains a number of
+   The netlist section contains a number of ``<module>``... ``</module>``
-   ``<module>``\ ... ``</module>`` elements, each describing the
+   elements, each describing the contents of that module, and a single
-   contents of that module, and a single ``<typetable>``\ ...
+   ``<typetable>``... ``</typetable>`` element which lists all used types
-   ``</typetable>`` element which lists all used types used within the
+   used within the modules. Each type has a numeric ``id`` attribute that
-   modules. Each type has a numeric ``id`` attribute that is referred to
+   is referred to by elements in the ``<module>`` elements using the
-   by elements in the ``<module>`` elements using the ``dtype_id``
+   ``dtype_id`` attribute.
-   attribute.
 
 
 Distribution
 ============
 
-Copyright 2020-2025 by Wilson Snyder. Verilator is free software; you can
+Copyright 2020-2026 by Wilson Snyder. Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser
 General Public License Version 3 or the Perl Artistic License Version 2.0.
 

examples/json_py/sub.v

@@ -5,12 +5,12 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module sub
+module sub #(
-  #(parameter type TYPE_t = logic)
+    parameter type TYPE_t = logic
-  (
+) (
     input TYPE_t in,
     output TYPE_t out
-   );
+);
 
   // Some simple logic
   always_comb out = ~in;

examples/json_py/top.v

@@ -5,8 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module top
+module top (
-  (
     input clk,
     input fastclk,
     input reset_l,
@@ -17,17 +16,26 @@ module top
     input [1:0] in_small,
     input [39:0] in_quad,
     input [69:0] in_wide
+);
+
+  sub #(
+      .TYPE_t(logic [1:0])
+  ) sub_small (
+      .in(in_small),
+      .out(out_small)
   );
 
-   sub #(.TYPE_t(logic [1:0])) sub_small
+  sub #(
-     (.in(in_small),
+      .TYPE_t(logic [39:0])
-      .out(out_small));
+  ) sub_quad (
+      .in(in_quad),
+      .out(out_quad)
+  );
 
-   sub #(.TYPE_t(logic [39:0])) sub_quad
+  sub #(
-     (.in(in_quad),
+      .TYPE_t(logic [69:0])
-      .out(out_quad));
+  ) sub_wide (
-
+      .in(in_wide),
-   sub #(.TYPE_t(logic [69:0])) sub_wide
+      .out(out_wide)
-     (.in(in_wide),
+  );
-      .out(out_wide));
 endmodule

examples/make_protect_lib/secret_impl.v

@@ -7,13 +7,13 @@
 // This module will be used as libsecret.a or libsecret.so without
 // exposing the source.
 
-module secret_impl
+module secret_impl (
-  (
     input [31:0] a,
     input [31:0] b,
     output logic [31:0] x,
     input clk,
-   input          reset_l);
+    input reset_l
+);
 
   logic [31:0] accum_q;
   logic [31:0] secret_value;
@@ -27,10 +27,8 @@ module secret_impl
     end
     else begin
       accum_q <= accum_q + a;
-      if (accum_q > 10)
+      if (accum_q > 10) x <= b;
-        x <= b;
+      else x <= a + b + secret_value;
-      else
-        x <= a + b + secret_value;
     end
   end
 

examples/make_protect_lib/top.v

@@ -6,7 +6,9 @@
 
 // See also https://verilator.org/guide/latest/examples.html"
 
-module top (input clk);
+module top (
+    input clk
+);
 
   int cyc;
   logic reset_l;
@@ -14,7 +16,13 @@ module top (input clk);
   logic [31:0] b;
   logic [31:0] x;
 
-  verilated_secret secret (.a, .b, .x, .clk, .reset_l);
+  verilated_secret secret (
+      .a,
+      .b,
+      .x,
+      .clk,
+      .reset_l
+  );
 
   always @(posedge clk) begin
     $display("[%0t] cyc=%0d a=%0d b=%0d x=%0d", $time, cyc, a, b, x);

examples/make_tracing_c/sim_main.cpp

@@ -38,6 +38,10 @@ int main(int argc, char** argv) {
     // May be overridden by commandArgs argument parsing
     contextp->debug(0);
 
+    // Peak number of threads the model will use
+    // (e.g. match the --threads setting of the Verilation)
+    contextp->threads(1);
+
     // Randomization reset policy
     // May be overridden by commandArgs argument parsing
     contextp->randReset(2);

examples/make_tracing_c/sub.v

@@ -5,11 +5,10 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module sub
+module sub (
-  (
     input clk,
     input reset_l
-   );
+);
 
   // Example counter/flop
   reg [31:0] count_c;

examples/make_tracing_c/top.v

@@ -8,8 +8,7 @@
 // This is intended to be a complex example of several features, please also
 // see the simpler examples/make_hello_c.
 
-module top
+module top (
-  (
     // Declare some signals so we can see how I/O works
     input clk,
     input reset_l,
@@ -20,7 +19,7 @@ module top
     input [1:0] in_small,
     input [39:0] in_quad,
     input [69:0] in_wide
-   );
+);
 
   // Connect up the outputs, using some trivial logic
   assign out_small = ~reset_l ? '0 : (in_small + 2'b1);

examples/make_tracing_sc/sub.v

@@ -5,12 +5,11 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module sub
+module sub (
-  (
     input clk,
     input fastclk,
     input reset_l
-   );
+);
 
   // Example counter/flop
   reg [31:0] count_f;

examples/make_tracing_sc/top.v

@@ -8,8 +8,7 @@
 // This is intended to be a complex example of several features, please also
 // see the simpler examples/make_hello_c.
 
-module top
+module top (
-  (
     // Declare some signals so we can see how I/O works
     input clk,
     input fastclk,
@@ -21,7 +20,7 @@ module top
     input [1:0] in_small,
     input [39:0] in_quad,
     input [69:0] in_wide
-   );
+);
 
   // Connect up the outputs, using some trivial logic
   assign out_small = ~reset_l ? '0 : (in_small + 2'b1);

include/verilated.cpp

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2025 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -3415,18 +3415,6 @@ VerilatedModel::VerilatedModel(VerilatedContext& context)
 
 std::unique_ptr<VerilatedTraceConfig> VerilatedModel::traceConfig() const { return nullptr; }
 
-//===========================================================================
-// VerilatedModule:: Methods
-
-VerilatedModule::VerilatedModule(const char* namep)
-    : m_namep{strdup(namep)} {}
-
-VerilatedModule::~VerilatedModule() {
-    // Memory cleanup - not called during normal operation
-    // cppcheck-suppress cstyleCast  // NOLINTNEXTLINE(google-readability-casting)
-    if (m_namep) VL_DO_CLEAR(free((void*)(m_namep)), m_namep = nullptr);
-}
-
 //======================================================================
 // VerilatedVar:: Methods
 
@@ -3466,37 +3454,36 @@ void* VerilatedVarProps::datapAdjustIndex(void* datap, int dim, int indx) const
 //======================================================================
 // VerilatedScope:: Methods
 
-VerilatedScope::~VerilatedScope() {
+VerilatedScope::VerilatedScope(VerilatedSyms* symsp, const char* suffixp, const char* identifier,
-    // Memory cleanup - not called during normal operation
+                               const char* defnamep, int8_t timeunit, Type type)
-    Verilated::threadContextp()->impp()->scopeErase(this);
+    : m_symsp{symsp}
-    if (m_namep) VL_DO_CLEAR(delete[] m_namep, m_namep = nullptr);
+    , m_namep{[symsp, suffixp]() {
-    if (m_callbacksp) VL_DO_CLEAR(delete[] m_callbacksp, m_callbacksp = nullptr);
-    if (m_varsp) VL_DO_CLEAR(delete m_varsp, m_varsp = nullptr);
-    m_funcnumMax = 0;  // Force callback table to empty
-}
-
-void VerilatedScope::configure(VerilatedSyms* symsp, const char* prefixp, const char* suffixp,
-                               const char* identifier, const char* defnamep, int8_t timeunit,
-                               const Type& type) VL_MT_UNSAFE {
-    // Slowpath - called once/scope at construction
         // We don't want the space and reference-count access overhead of strings.
-    m_symsp = symsp;
+        const char* prefixp = symsp->name();
-    m_type = type;
-    m_timeunit = timeunit;
-    {
         char* const namep = new char[std::strlen(prefixp) + std::strlen(suffixp) + 2];
         char* dp = namep;
         for (const char* sp = prefixp; *sp;) *dp++ = *sp++;
         if (*prefixp && *suffixp) *dp++ = '.';
         for (const char* sp = suffixp; *sp;) *dp++ = *sp++;
         *dp++ = '\0';
-        m_namep = namep;
+        return namep;
-    }
+    }()}
-    m_identifierp = identifier;
+    , m_identifierp{identifier}
-    m_defnamep = defnamep;
+    , m_defnamep{defnamep}
+    , m_timeunit{timeunit}
+    , m_type{type} {
     Verilated::threadContextp()->impp()->scopeInsert(this);
 }
 
+VerilatedScope::~VerilatedScope() {
+    // Memory cleanup - not called during normal operation
+    Verilated::threadContextp()->impp()->scopeErase(this);
+    VL_DO_DANGLING(delete[] m_namep, m_namep);
+    VL_DO_DANGLING(delete[] m_callbacksp, m_callbacksp);
+    VL_DO_DANGLING(delete m_varsp, m_varsp);
+    VL_DEBUG_IFDEF(m_funcnumMax = 0;);
+}
+
 void VerilatedScope::exportInsert(int finalize, const char* namep, void* cb) VL_MT_UNSAFE {
     // Slowpath - called once/scope*export at construction
     // Insert a exported function into scope table
@@ -3518,13 +3505,12 @@ void VerilatedScope::exportInsert(int finalize, const char* namep, void* cb) VL_
     }
 }
 
-void VerilatedScope::varInsert(int finalize, const char* namep, void* datap, bool isParam,
+void VerilatedScope::varInsert(const char* namep, void* datap, bool isParam,
                                VerilatedVarType vltype, int vlflags, int udims,
                                int pdims...) VL_MT_UNSAFE {
     // Grab dimensions
     // In the future we may just create a large table at emit time and
     // statically construct from that.
-    if (!finalize) return;
 
     if (!m_varsp) m_varsp = new VerilatedVarNameMap;
     VerilatedVar var(namep, datap, vltype, static_cast<VerilatedVarFlags>(vlflags), udims, pdims,
@@ -3598,6 +3584,8 @@ void VerilatedHierarchy::remove(const VerilatedScope* fromp, const VerilatedScop
     VerilatedImp::hierarchyRemove(fromp, top);
 }
 
+void VerilatedHierarchy::clear() { VerilatedImp::hierarchyClear(); }
+
 //===========================================================================
 // VerilatedOneThreaded:: Methods
 

include/verilated.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2025 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -154,7 +154,8 @@ enum VerilatedVarFlags {
     // Flags
     VLVF_PUB_RD = (1 << 8),  // Public readable
     VLVF_PUB_RW = (1 << 9),  // Public writable
-    VLVF_DPI_CLAY = (1 << 10)  // DPI compatible C standard layout
+    VLVF_DPI_CLAY = (1 << 10),  // DPI compatible C standard layout
+    VLVF_SIGNED = (1 << 11)  // Signed integer
 };
 
 // IEEE 1800-2023 Table 20-6
@@ -308,20 +309,6 @@ private:
     virtual std::unique_ptr<VerilatedTraceConfig> traceConfig() const;
 };
 
-//=========================================================================
-/// Base class for all Verilated module classes.
-
-class VerilatedModule VL_NOT_FINAL {
-    VL_UNCOPYABLE(VerilatedModule);
-
-private:
-    const char* m_namep;  // Module name
-public:
-    explicit VerilatedModule(const char* namep);  // Create module with given hierarchy name
-    ~VerilatedModule();
-    const char* name() const VL_MT_SAFE_POSTINIT { return m_namep; }  ///< Return name of module
-};
-
 //=========================================================================
 // Functions overridable by user defines
 // (Internals however must use VL_PRINTF_MT, which calls these.)
@@ -694,6 +681,8 @@ public:  // But for internal use only
     explicit VerilatedSyms(VerilatedContext* contextp);  // Pass null for default context
     ~VerilatedSyms();
     VL_UNCOPYABLE(VerilatedSyms);
+
+    virtual const char* name() const = 0;
 };
 
 //===========================================================================
@@ -709,26 +698,25 @@ public:
     };  // Type of a scope, currently only module and package are interesting
 private:
     // Fastpath:
-    VerilatedSyms* m_symsp = nullptr;  // Symbol table
+    VerilatedSyms* const m_symsp;  // Symbol table
     void** m_callbacksp = nullptr;  // Callback table pointer (Fastpath)
     int m_funcnumMax = 0;  // Maximum function number stored (Fastpath)
     // 4 bytes padding (on -m64), for rent.
     VerilatedVarNameMap* m_varsp = nullptr;  // Variable map
-    const char* m_namep = nullptr;  // Scope name (Slowpath)
+    const char* const m_namep;  // Scope name (Slowpath)
-    const char* m_identifierp = nullptr;  // Identifier of scope (with escapes removed)
+    const char* const m_identifierp;  // Identifier of scope (with escapes removed)
-    const char* m_defnamep = nullptr;  // Definition name (SCOPE_MODULE only)
+    const char* const m_defnamep;  // Definition name (SCOPE_MODULE only)
-    int8_t m_timeunit = 0;  // Timeunit in negative power-of-10
+    const int8_t m_timeunit;  // Timeunit in negative power-of-10
-    Type m_type = SCOPE_OTHER;  // Type of the scope
+    const Type m_type;  // Type of the scope
 
-public:  // But internals only - called from VerilatedModule's
+public:  // But internals only - called from verilated modules, VerilatedSyms
-    VerilatedScope() = default;
+    VerilatedScope(VerilatedSyms* symsp, const char* suffixp, const char* identifier,
+                   const char* defnamep, int8_t timeunit, Type type);
     ~VerilatedScope();
-    void configure(VerilatedSyms* symsp, const char* prefixp, const char* suffixp,
+
-                   const char* identifier, const char* defnamep, int8_t timeunit,
-                   const Type& type) VL_MT_UNSAFE;
     void exportInsert(int finalize, const char* namep, void* cb) VL_MT_UNSAFE;
-    void varInsert(int finalize, const char* namep, void* datap, bool isParam,
+    void varInsert(const char* namep, void* datap, bool isParam, VerilatedVarType vltype,
-                   VerilatedVarType vltype, int vlflags, int udims, int pdims, ...) VL_MT_UNSAFE;
+                   int vlflags, int udims, int pdims, ...) VL_MT_UNSAFE;
     // ACCESSORS
     const char* name() const VL_MT_SAFE_POSTINIT { return m_namep; }
     const char* identifier() const VL_MT_SAFE_POSTINIT { return m_identifierp; }
@@ -756,6 +744,7 @@ class VerilatedHierarchy final {
 public:
     static void add(const VerilatedScope* fromp, const VerilatedScope* top);
     static void remove(const VerilatedScope* fromp, const VerilatedScope* top);
+    static void clear();
 };
 
 //===========================================================================
@@ -1039,18 +1028,13 @@ void VerilatedContext::timeprecision(int value) VL_MT_SAFE {
         m_s.m_timeprecision = value;
 #if VM_SC
         const sc_core::sc_time sc_res = sc_core::sc_get_time_resolution();
-        if (sc_res == sc_core::sc_time(1, sc_core::SC_SEC)) {
+        double mult = 1.0;
-            sc_prec = 0;
+        for (int i = 0; i < 16; i++) {
-        } else if (sc_res == sc_core::sc_time(1, sc_core::SC_MS)) {
+            if (sc_res == sc_core::sc_time(mult, sc_core::SC_FS)) {
-            sc_prec = 3;
+                sc_prec = 15 - i;
-        } else if (sc_res == sc_core::sc_time(1, sc_core::SC_US)) {
+                break;
-            sc_prec = 6;
+            }
-        } else if (sc_res == sc_core::sc_time(1, sc_core::SC_NS)) {
+            mult *= 10.0;
-            sc_prec = 9;
-        } else if (sc_res == sc_core::sc_time(1, sc_core::SC_PS)) {
-            sc_prec = 12;
-        } else if (sc_res == sc_core::sc_time(1, sc_core::SC_FS)) {
-            sc_prec = 15;
         }
         // SC_AS, SC_ZS, SC_YS not supported as no Verilog equivalent; will error below
 #endif

include/verilated.mk.in

@@ -2,7 +2,7 @@
 ######################################################################
 # DESCRIPTION: Makefile commands for all verilated target files
 #
-# Copyright 2003-2025 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2026 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -262,7 +262,7 @@ endif
 
 # Truncate the dependency list file used in the %.a target above.
 %.verilator_deplist.tmp:
-	echo "" > $@
+	@echo "" > $@
 
 $(VM_PREFIX)__ALL.a: $(VK_OBJS) $(VM_HIER_LIBS)
 
@@ -311,30 +311,27 @@ ifneq ($(findstring ccache-report,$(MAKECMDGOALS)),)
   endif
   VK_OTHER_GOALS := $(strip $(subst ccache-report,,$(MAKECMDGOALS)))
   ifeq ($(VK_OTHER_GOALS),)
-    $(error ccache-report must be used with at least one other explicit target)
+    VK_OTHER_GOALS := default
   endif
 
   # Report ccache behaviour for this invocation of make
   VK_CCACHE_LOGDIR := ccache-logs
   VK_CCACHE_REPORT := $(VM_PREFIX)__ccache_report.txt
-  # Remove previous logfiles and report
+
+  # Remove previous logfiles and report, then create log directory
   $(shell rm -rf $(VK_CCACHE_LOGDIR) $(VK_CCACHE_REPORT))
+  $(shell mkdir -p $(VK_CCACHE_LOGDIR))
 
-  $(VK_CCACHE_LOGDIR):
+  # Add ccache logging to compilation rules
-	mkdir -p $@
-
-  $(VK_OBJS): | $(VK_CCACHE_LOGDIR)
-
   $(VK_OBJS): export CCACHE_LOGFILE=$(VK_CCACHE_LOGDIR)/$@.log
 
-  $(VK_CCACHE_REPORT): $(VK_OBJS)
+  # ccache-report runs last
+  $(VK_CCACHE_REPORT): $(VK_OBJS) $(VK_OTHER_GOALS)
 	$(VERILATOR_CCACHE_REPORT) -o $@ $(VK_CCACHE_LOGDIR)
 
-  # ccache-report runs last
   .PHONY: ccache-report
-  ccache-report: $(VK_CCACHE_REPORT) $(VK_OTHER_GOALS)
+  ccache-report: $(VK_CCACHE_REPORT)
 	@cat $<
-
 endif
 
 ######################################################################

include/verilated.v

@@ -2,7 +2,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2025 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_config.h.in

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2025 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_cov.cpp

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2025 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2026 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_cov.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2025 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2026 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_cov_key.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2025 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2026 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_dpi.cpp

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2009-2025 by Wilson Snyder. This program is free software; you can
+// Copyright 2009-2026 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_dpi.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2025 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_fst_c.cpp

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2025 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2026 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -149,8 +149,9 @@ static std::pair<bool, fstScopeType> toFstScopeType(VerilatedTracePrefixType typ
     }
 }
 
-void VerilatedFst::pushPrefix(const std::string& name, VerilatedTracePrefixType type) {
+void VerilatedFst::pushPrefix(const char* namep, VerilatedTracePrefixType type) {
     assert(!m_prefixStack.empty());  // Constructor makes an empty entry
+    const std::string name{namep};
     // An empty name means this is the root of a model created with
     // name()=="".  The tools get upset if we try to pass this as empty, so
     // we put the signals under a new $rootio scope, but the signals

include/verilated_fst_c.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2025 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2026 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -110,7 +110,7 @@ public:
     //=========================================================================
     // Internal interface to Verilator generated code
 
-    void pushPrefix(const std::string&, VerilatedTracePrefixType);
+    void pushPrefix(const char*, VerilatedTracePrefixType);
     void popPrefix();
 
     void declEvent(uint32_t code, uint32_t fidx, const char* name, int dtypenum,

include/verilated_fst_sc.cpp

@@ -3,7 +3,7 @@
 //
 // THIS MODULE IS PUBLICLY LICENSED
 //
-// Copyright 2001-2025 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2026 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_fst_sc.h

@@ -1,7 +1,7 @@
 // -*- mode: C++; c-file-style: "cc-mode" -*-
 //=============================================================================
 //
-// Copyright 2001-2025 by Wilson Snyder. This program is free software; you can
+// Copyright 2001-2026 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_funcs.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2025 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -490,6 +490,10 @@ static inline void VL_ASSIGNBIT_WO(int bit, WDataOutP owp) VL_MT_SAFE {
     { (vvar) = VL_CLEAN_II((obits), (obits), (svar).read().to_uint()); }
 #define VL_ASSIGN_QSU(obits, vvar, svar) \
     { (vvar) = VL_CLEAN_QQ((obits), (obits), (svar).read().to_uint64()); }
+#define VL_ASSIGN_ISB(obits, vvar, svar) \
+    { (vvar) = VL_CLEAN_II((obits), (obits), (svar).read().to_uint()); }
+#define VL_ASSIGN_QSB(obits, vvar, svar) \
+    { (vvar) = VL_CLEAN_QQ((obits), (obits), (svar).read().to_uint64()); }
 #define VL_ASSIGN_WSB(obits, owp, svar) \
     { \
         const int words = VL_WORDS_I(obits); \

include/verilated_imp.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2009-2025 by Wilson Snyder. This program is free software; you can
+// Copyright 2009-2026 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -524,6 +524,11 @@ public:
         const auto it = find(scopes.begin(), scopes.end(), top);
         if (it != scopes.end()) scopes.erase(it);
     }
+    static void hierarchyClear() VL_MT_SAFE {
+        const VerilatedLockGuard lock{s().m_hierMapMutex};
+        VerilatedHierarchyMap& map = s().m_hierMap;
+        map.clear();
+    }
     static const VerilatedHierarchyMap* hierarchyMap() VL_MT_SAFE_POSTINIT {
         // Thread save only assuming this is called only after model construction completed
         return &s().m_hierMap;

include/verilated_intrinsics.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2025 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.