luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Restore Antmicro copyright on test files accidentally overwritten

This commit is contained in:
Yilou Wang 2026-06-15 14:31:52 +02:00
parent 969a775ae5
commit 7dbce60884
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
test_regress/t/t_constraint_unsup.v
View File

@ -1,7 +1,7 @@
// DESCRIPTION: Verilator: Verilog Test module // DESCRIPTION: Verilator: Verilog Test module
// //
// This file ONLY is placed under the Creative Commons Public Domain. // This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 PlanV GmbH // SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
class Packet; class Packet;

2
test_regress/t/t_property_sexpr_multi.v
View File

@ -1,7 +1,7 @@
// DESCRIPTION: Verilator: Verilog Test module // DESCRIPTION: Verilator: Verilog Test module
// //
// This file ONLY is placed under the Creative Commons Public Domain. // This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 PlanV GmbH // SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off // verilog_format: off