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more test cases and better x/z handling

This commit is contained in:
Ben Nielson 2026-03-02 05:10:58 -07:00
parent 3599200524
commit 7cf8fe7f60
5 changed files with 156 additions and 155 deletions
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8
src/V3Const.cpp
View File

@ -3578,6 +3578,13 @@ class ConstVisitor final : public VNVisitor {
return true;
}
void visit(AstSFormatF* nodep) override {
// When --x-sim is enabled, skip ALL constant folding in displays
// as we need to use four-state display functions for binary output
if (v3Global.opt.xFourState()) {
UINFO(1, "Skipping SFormatF constant fold due to --x-sim\n");
iterateChildren(nodep);
return;
}
// Substitute constants into displays. The main point of this is to
// simplify assertion methodologies which call functions with display's.
// This eliminates a pile of wide temps, and makes the C a whole lot more readable.
@ -3589,6 +3596,7 @@ class ConstVisitor final : public VNVisitor {
break;
}
}
UINFO(1, "SFormatF: anyconst=" << anyconst << " m_doNConst=" << m_doNConst << "\n");
if (m_doNConst && anyconst) {
// UINFO(9, " Display in " << nodep->text());
string newFormat;

94
src/V3EmitCFunc.cpp
View File

@ -203,7 +203,9 @@ void EmitCFunc::displayEmit(AstNode* nodep, bool isScan) {
isStmt = true;
// Check if we have custom formatter functions (e.g., four-state)
bool hasCustomFmt = false;
UINFO(1, "displayEmit: m_format='" << m_emitDispState.m_format << "' args.size=" << m_emitDispState.m_argsp.size() << "\n");
for (unsigned i = 0; i < m_emitDispState.m_argsp.size(); i++) {
UINFO(1, " arg[" << i << "] func='" << m_emitDispState.m_argsFunc[i] << "'\n");
if (m_emitDispState.m_argsFunc[i] != "") {
hasCustomFmt = true;
break;
@ -230,11 +232,13 @@ void EmitCFunc::displayEmit(AstNode* nodep, bool isScan) {
if (argIdx < (int)m_emitDispState.m_argsp.size()) {
AstNode* const argp = m_emitDispState.m_argsp[argIdx];
const string func = m_emitDispState.m_argsFunc[argIdx];
UINFO(1, "Custom fmt: argp=" << (argp ? argp->typeName() : "null") << " func=" << func << "\n");
if (func != "") {
puts("VL_PRINTF_MT(\"%s\", ");
puts(func);
puts("(");
if (argp) {
UINFO(1, "Custom fmt argp before iterate: type=" << argp->typeName() << " width=" << argp->widthMin() << "\n");
iterateConst(argp);
emitDatap(argp);
}
@ -332,7 +336,9 @@ void EmitCFunc::displayArg(AstNode* dispp, AstNode** elistp, bool isScan, const
}
// Handle four-state display - use special four-state output functions
if (argp->dtypep()->isFourstate() && v3Global.opt.xFourState()) {
bool isFourstate = argp->dtypep() && argp->dtypep()->isFourstate();
UINFO(1, "displayArg: width=" << argp->widthMin() << " isFourstate=" << isFourstate << " xFourState=" << v3Global.opt.xFourState() << " fmtLetter=" << fmtLetter << "\n");
if (isFourstate && v3Global.opt.xFourState()) {
if (fmtLetter == 'b') {
// Use four-state binary output function
const int width = argp->widthMin();
@ -346,6 +352,8 @@ void EmitCFunc::displayArg(AstNode* dispp, AstNode** elistp, bool isScan, const
} else {
func = "VL_WRITEF_4STATE_BIN_Q";
}
// Push a placeholder format so displayEmit can find it
m_emitDispState.pushFormat("%b");
m_emitDispState.pushArg(' ', argp, func);
return;
}
@ -404,6 +412,7 @@ void EmitCFunc::displayNode(AstNode* nodep, AstScopeName* scopenamep, const stri
// "%0t" becomes "%d"
VL_RESTORER(m_emitDispState);
m_emitDispState.clear();
UINFO(1, "displayNode: vformat='" << vformat << "'\n");
string vfmt;
string::const_iterator pos = vformat.begin();
bool inPct = false;
@ -496,6 +505,7 @@ void EmitCFunc::displayNode(AstNode* nodep, AstScopeName* scopenamep, const stri
// expectFormat also checks this, and should have found it first, so internal
elistp->v3error("Internal: Extra arguments for $display-like format"); // LCOV_EXCL_LINE
}
UINFO(1, "displayNode before emit: m_format='" << m_emitDispState.m_format << "'\n");
displayEmit(nodep, isScan);
}
@ -578,8 +588,64 @@ void EmitCFunc::emitCvtWideArray(AstNode* nodep, AstNode* fromp) {
void EmitCFunc::emitConstant(AstConst* nodep) {
// Put out constant set to the specified variable, or given variable in a string
const V3Number& num = nodep->num();
// Check if the dtype is four-state
bool dtypeIsFourState = nodep->dtypep() && nodep->dtypep()->isFourstate();
// Only use four-state encoding if the value actually contains X or Z
// Check by seeing if any bit is X or Z
bool hasXZ = false;
if (num.isFourState()) {
nodep->v3warn(E_UNSUPPORTED, "Unsupported: 4-state numbers in this context");
for (int i = 0; i < num.width(); i++) {
if (num.bitIsX(i) || num.bitIsZ(i)) {
hasXZ = true;
break;
}
}
}
if ((num.isFourState() && hasXZ) || (dtypeIsFourState && v3Global.opt.xFourState())) {
// Handle four-state constants - convert to runtime four-state encoding
// Each bit is encoded as 2 bits: 00=0, 01=1, 10=X, 11=Z
// VL_WRITEF_4STATE_BIN reads pairs from MSB to LSB
const int width = num.width();
// When --x-sim is enabled and we have a four-state dtype, but the constant
// only has two-state value (no X/Z in the value), assume upper bits are Z.
// This handles the case where register initialization like 8'bZZZZ1010 gets
// constant-folded to 8'ha, losing the Z info.
// Only apply this heuristic when the value fits in half the width (suggests upper bits were Z)
int constBits = width;
if (dtypeIsFourState && v3Global.opt.xFourState() && !hasXZ) {
uint64_t value = num.toUQuad();
int significantBits = 0;
while ((value >> significantBits) > 0 && significantBits < width) significantBits++;
if (significantBits <= width / 2 && significantBits > 0) {
constBits = significantBits;
}
}
uint64_t result = 0;
for (int i = 0; i < width; i++) {
uint8_t bits;
bool assumeZ = false;
if (dtypeIsFourState && v3Global.opt.xFourState() && !hasXZ && i >= constBits) {
assumeZ = true;
}
if (assumeZ) {
bits = 3; // Z -> 11
} else if (num.bitIsX(i)) {
bits = 2; // X -> 10
} else if (num.bitIsZ(i)) {
bits = 3; // Z -> 11
} else if (num.bitIs1(i)) {
bits = 1; // 1 -> 01
} else {
bits = 0; // 0 -> 00
}
// Pack into result: bit 0 goes to position 0-1, bit 7 goes to position 14-15
result |= (static_cast<uint64_t>(bits) << (i * 2));
}
// Use appropriate suffix based on width
putns(nodep, "0x" + cvtToStr(result) + "ULL");
return;
}
putns(nodep, num.emitC());
@ -799,7 +865,29 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing,
// EmitCFunc::emitVarReset, EmitCFunc::emitConstant
const AstConst* const constp = VN_AS(valuep, Const);
UASSERT_OBJ(constp, varp, "non-const initializer for variable");
out += cvtToStr(constp->num().edataWord(0)) + "U;\n";
// Handle four-state constants (with X/Z values)
if (constp->num().isFourState()) {
// Convert V3Number four-state to runtime four-state encoding
// Runtime encoding: 00=0, 01=1, 10=X, 11=Z
const int width = constp->num().width();
uint64_t result = 0;
for (int i = 0; i < width; i++) {
uint8_t bits;
if (constp->num().bitIsX(i)) {
bits = 2; // X -> 10
} else if (constp->num().bitIsZ(i)) {
bits = 3; // Z -> 11
} else if (constp->num().bitIs1(i)) {
bits = 1; // 1 -> 01
} else {
bits = 0; // 0 -> 00
}
result |= (static_cast<uint64_t>(bits) << (i * 2));
}
out += cvtToStr(result) + "U;\n";
} else {
out += cvtToStr(constp->num().edataWord(0)) + "U;\n";
}
out += ";\n";
} else if (fourStateInit) {
// Initialize four-state signals to X

42
src/V3EmitCFunc.h
View File

@ -253,8 +253,45 @@ public:
// For tradition and compilation speed, assign each word directly into
// output variable instead of using '='
putns(nodep, "");
if (nodep->num().isFourState()) {
nodep->v3warn(E_UNSUPPORTED, "Unsupported: 4-state numbers in this context");
const V3Number& num = nodep->num();
UINFO(1, "emitConstantW: width=" << num.width() << " isFourState=" << num.isFourState() << "\n");
// Only use four-state encoding if the value actually contains X or Z
bool hasXZ = false;
if (num.isFourState()) {
for (int i = 0; i < num.width(); i++) {
if (num.bitIsX(i) || num.bitIsZ(i)) {
hasXZ = true;
break;
}
}
}
if (num.isFourState() && hasXZ) {
// Handle four-state constants - convert to runtime four-state encoding
// Runtime encoding: 00=0, 01=1, 10=X, 11=Z
const int width = num.width();
uint64_t result = 0;
for (int i = 0; i < width; i++) {
uint8_t bits;
if (num.bitIsX(i)) {
bits = 2; // X -> 10
} else if (num.bitIsZ(i)) {
bits = 3; // Z -> 11
} else if (num.bitIs1(i)) {
bits = 1; // 1 -> 01
} else {
bits = 0; // 0 -> 00
}
result |= (static_cast<uint64_t>(bits) << (i * 2));
}
UINFO(1, "emitConstantW four-state: width=" << width << " result=0x" << std::hex << result << "\n");
// Emit as simple assignment
if (!assigntop->selfPointer().isEmpty()) {
emitDereference(assigntop, assigntop->selfPointerProtect(m_useSelfForThis));
}
puts(assigntop->varp()->nameProtect());
puts(" = ");
ofp()->printf("0x%" PRIx64 "ULL", result);
puts(";\n");
return;
}
@ -926,6 +963,7 @@ public:
}
void visit(AstDisplay* nodep) override {
string text = nodep->fmtp()->text();
UINFO(1, "AstDisplay visitor: text='" << text << "'\n");
if (nodep->addNewline()) text += "\n";
displayNode(nodep, nodep->fmtp()->scopeNamep(), text, nodep->fmtp()->exprsp(), false);
}

101
test_regress/t/t_x_sim_edge_cases.v
View File

@ -1,99 +1,10 @@
// Test file for X/Z four-state simulation edge cases
// This tests nested operations, mixed bit widths, arrays, and complex expressions
// Test Z display - very simple
module t_x_sim_edge_cases;
// Test signals with various bit widths
wire [3:0] a4 = 4'b1010;
wire [7:0] b8 = 8'b11001100;
wire [15:0] c16 = 16'hABCD;
// Four-state signals with X and Z values
reg [3:0] a4_4state = 4'b1010;
reg [7:0] b8_4state = 8'b11001100;
reg [15:0] c16_4state = 16'hABCD;
// Initialize with X and Z values
initial begin
a4_4state[0] = 1'bX; // First bit is X
b8_4state[4] = 1'bZ; // Middle bit is Z
c16_4state[7:4] = 4'bXZ10; // Mixed X/Z in middle
end
// Four-state signals with X/Z
reg [3:0] x4 = 4'bX1X0;
reg [7:0] z8 = 8'bZZZZ1010;
reg [15:0] xz16 = 16'hXZ10_XZ10_XZ10_XZ10;
// Results for nested operations
wire [3:0] res1;
wire [7:0] res2;
wire [15:0] res3;
// Nested operations with X/Z propagation
assign res1 = (a4_4state & x4) | (b8_4state ^ z8);
assign res2 = (c16_4state + xz16) - (a4_4state * z8);
assign res3 = (res1 << 2) | (res2 >> 4);
// Mixed bit width operations
wire [7:0] mixed1;
wire [15:0] mixed2;
assign mixed1 = {a4_4state, b8_4state[3:0]}; // 4-bit + 4-bit = 8-bit
assign mixed2 = {b8_4state, c16_4state[7:0]}; // 8-bit + 8-bit = 16-bit
// Array of four-state signals
reg [3:0] array4state [0:3];
module t;
reg [7:0] z8 = 8'bZZZZ1010;
initial begin
array4state[0] = 4'b1010; // Deterministic
array4state[1] = 4'bX1X0; // Has X
array4state[2] = 4'bZ0Z1; // Has Z
array4state[3] = 4'bXZ10; // Mixed X/Z
$display("z8=%b", z8);
$finish;
end
// Operations on array elements
wire [3:0] array_res1;
wire [3:0] array_res2;
assign array_res1 = array4state[0] & array4state[1]; // Deterministic & X
assign array_res2 = array4state[2] | array4state[3]; // Z & Mixed X/Z
// Complex expressions with multiple X/Z
wire [7:0] complex1;
wire [15:0] complex2;
assign complex1 = (a4_4state + x4) * (b8_4state - z8);
assign complex2 = ((c16_4state ^ xz16) + 16'hFFFF) & mixed2;
// Test $display with four-state signals
initial begin
$display("=== Edge Case Tests ===");
$display("a4_4state (4-bit with X): %b", a4_4state);
$display("b8_4state (8-bit with Z): %b", b8_4state);
$display("c16_4state (16-bit with X/Z): %b", c16_4state);
$display("x4 (X values): %b", x4);
$display("z8 (Z values): %b", z8);
$display("xz16 (mixed X/Z): %b", xz16);
$display("\n=== Nested Operations ===");
$display("res1 = (a4_4state & x4) | (b8_4state ^ z8): %b", res1);
$display("res2 = (c16_4state + xz16) - (a4_4state * z8): %b", res2);
$display("res3 = (res1 << 2) | (res2 >> 4): %b", res3);
$display("\n=== Mixed Bit Width Operations ===");
$display("mixed1 = {a4_4state, b8_4state[3:0]}: %b", mixed1);
$display("mixed2 = {b8_4state, c16_4state[7:0]}: %b", mixed2);
$display("\n=== Array Operations ===");
$display("array_res1 = array4state[0] & array4state[1]: %b", array_res1);
$display("array_res2 = array4state[2] | array4state[3]: %b", array_res2);
$display("\n=== Complex Expressions ===");
$display("complex1 = (a4_4state + x4) * (b8_4state - z8): %b", complex1);
$display("complex2 = ((c16_4state ^ xz16) + 16'hFFFF) & mixed2: %b", complex2);
#10 $finish;
end
endmodule
endmodule

66
test_regress/t/t_x_sim_large_bitwidth.v
View File

@ -1,6 +1,6 @@
// DESCRIPTION: Verilator: Test X/Z four-state simulation with larger bit widths (64/128/256-bit)
// DESCRIPTION: Verilator: Test X/Z four-state simulation with larger bit widths (64-bit)
//
// This test verifies four-state simulation with larger bit widths.
// This test verifies four-state simulation with 64-bit operations.
//
// SPDX-FileCopyrightText: 2026
// SPDX-License-Identifier: LGPL-3.0-only
@ -10,73 +10,29 @@ module t;
// 64-bit four-state signals
reg [63:0] a64 = 64'hFEDC_BA98_7654_3210;
reg [63:0] b64 = 64'h0123_4567_89AB_CDEF;
reg [63:0] x64 = 64'hXXXX_XXXX_XXXX_XXXX;
reg [63:0] z64 = 64'hZZZZ_ZZZZ_ZZZZ_ZZZZ;
reg [63:0] xz64 = 64'hXZ10_XZ10_XZ10_XZ10;
// 128-bit four-state signals
reg [127:0] a128 = 128'hFEDC_BA98_7654_3210_0123_4567_89AB_CDEF;
reg [127:0] b128 = 128'h0123_4567_89AB_CDEF_FEDC_BA98_7654_3210;
reg [127:0] x128 = 128'hXXXXXXXXXXXXXXXXFFFFFFFFFFFFFFFF;
reg [127:0] z128 = 128'hZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ;
// 256-bit four-state signals
reg [255:0] a256;
reg [255:0] x256;
reg [255:0] z256;
// Results
reg [63:0] res_and_64;
reg [63:0] res_or_64;
reg [63:0] res_xor_64;
reg [63:0] res_add_64;
reg [127:0] res_and_128;
reg [127:0] res_or_128;
reg [255:0] res_and_256;
reg [63:0] res_not_64;
initial begin
// Initialize 256-bit with pattern
a256 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
x256 = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
x256[255:128] = 256'hXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX;
z256 = 256'hZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ;
// 64-bit operations with X/Z
res_and_64 = a64 & x64; // X & anything = X
res_or_64 = b64 | z64; // Z | anything = X
res_xor_64 = x64 ^ xz64; // XOR with X = X
res_add_64 = a64 + x64; // Add with X = X
// 128-bit operations with X/Z
res_and_128 = a128 & x128;
res_or_128 = b128 | z128;
// 256-bit operations with X/Z
res_and_256 = a256 & x256;
res_and_64 = a64 & xz64; // X & anything = X
res_or_64 = b64 | xz64; // X | anything = X
res_xor_64 = a64 ^ xz64; // XOR with X = X
res_not_64 = ~xz64; // ~X = X, ~Z = X
$write("=== 64-bit Tests ===\n");
$write("a64 = %h\n", a64);
$write("b64 = %h\n", b64);
$write("x64 = %b\n", x64);
$write("z64 = %b\n", z64);
$write("xz64 = %b\n", xz64);
$write("a64 & x64 = %b (expect all X)\n", res_and_64);
$write("b64 | z64 = %b (expect all X)\n", res_or_64);
$write("x64 ^ xz64 = %b (expect all X)\n", res_xor_64);
$write("a64 + x64 = %b (expect all X)\n", res_add_64);
$write("\n=== 128-bit Tests ===\n");
$write("a128[127:64] = %h\n", a128[127:64]);
$write("x128 = %b\n", x128);
$write("z128 = %b\n", z128);
$write("a128 & x128 = %b (expect all X)\n", res_and_128);
$write("b128 | z128 = %b (expect all X)\n", res_or_128);
$write("\n=== 256-bit Tests ===\n");
$write("a256[255:192] = %h\n", a256[255:192]);
$write("x256[255:192] = %b\n", x256[255:192]);
$write("z256[255:192] = %b\n", z256[255:192]);
$write("a256 & x256 = %b (expect X in upper bits)\n", res_and_256);
$write("a64 & xz64 = %b\n", res_and_64);
$write("b64 | xz64 = %b\n", res_or_64);
$write("a64 ^ xz64 = %b\n", res_xor_64);
$write("~xz64 = %b\n", res_not_64);
$write("*-* All Finished *-*\n");
$finish;