more tests and fixes
This commit is contained in:
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de0236be2f
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7a9563db57
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@ -2178,6 +2178,50 @@ public:
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});
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}
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// Resolve `class::member` Dots in `rootp`'s tree, and also in any deferred
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// lparam reachable transitively through VarRefs from `rootp`. By V3Param
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// time the surviving such Dots are paramed-class refs that need
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// linkDotParamed for scope, but `resolveDotToTypedef` can handle the
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// typedef-aliased subset inline. Resolving them here turns a deferred
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// lparam's value into a Const so subsequent constify on `rootp` can fold
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// expressions that reference the lparam.
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// `modp` is the enclosing module — resolveDotToTypedef may call into
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// classRefDeparam which needs m_modp set for level/recursion bookkeeping.
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void resolveDeferredDotsReachableFrom(AstNode* rootp, AstNodeModule* modp) {
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std::vector<AstDot*> dotps;
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const auto& deferredVarps = v3Global.rootp()->deferredParamVarps();
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std::set<AstVar*> reachedDeferred;
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auto collectDots = [&](AstNode* p) {
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p->foreach([&](AstDot* dotp) {
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if (VN_IS(dotp->lhsp(), ClassOrPackageRef)) dotps.push_back(dotp);
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});
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};
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std::vector<AstVar*> workVarps;
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auto enqueueRefs = [&](AstNode* p) {
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p->foreach([&](const AstVarRef* refp) {
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AstVar* const refVarp = refp->varp();
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if (refVarp && refVarp->varType() == VVarType::LPARAM
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&& deferredVarps.count(refVarp) && reachedDeferred.insert(refVarp).second) {
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workVarps.push_back(refVarp);
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}
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});
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};
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collectDots(rootp);
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enqueueRefs(rootp);
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while (!workVarps.empty()) {
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AstVar* const varp = workVarps.back();
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workVarps.pop_back();
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if (!varp->valuep()) continue;
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collectDots(varp->valuep());
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enqueueRefs(varp->valuep());
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}
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if (dotps.empty()) return;
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VL_RESTORER(m_modp);
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m_modp = modp;
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// Reverse-iterate so inner Dots resolve before outer.
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for (auto it = dotps.rbegin(); it != dotps.rend(); ++it) resolveDotToTypedef(*it);
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}
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AstNodeModule* nodeDeparam(AstNode* nodep, AstNodeModule* srcModp, AstNodeModule* modp,
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const string& someInstanceName) {
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// Return new or reused de-parameterized module
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@ -2218,14 +2262,9 @@ public:
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}
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// Create new module name with _'s between the constants
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UINFOTREE(10, nodep, "", "cell");
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// Resolve `class::member` Dots in pin values so constify sees Consts.
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// Single-pass: filter-collect class-scoped Dots, then reverse-iterate so inner
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// Dots resolve before outer (vector stays empty for cells with no class Dots).
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std::vector<AstDot*> dotps;
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nodep->foreach([&](AstDot* dotp) {
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if (VN_IS(dotp->lhsp(), ClassOrPackageRef)) dotps.push_back(dotp);
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});
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for (auto it = dotps.rbegin(); it != dotps.rend(); ++it) resolveDotToTypedef(*it);
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// Resolve `class::member` Dots in pin values, and in any deferred
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// lparam reachable from the pin tree, so constify sees Consts.
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resolveDeferredDotsReachableFrom(nodep, modp);
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// Evaluate all module constants
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V3Const::constifyParamsEdit(nodep);
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// Set name for warnings for when we param propagate the module
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@ -3173,6 +3212,9 @@ class ParamVisitor final : public VNVisitor {
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void visit(AstGenIf* nodep) override {
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UINFO(9, " GENIF " << nodep);
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iterateAndNextNull(nodep->condp());
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// condp may reference deferred lparams whose Dot is still pending;
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// resolve them so widthing/constify can see Consts.
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m_processor.resolveDeferredDotsReachableFrom(nodep->condp(), m_modp);
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// We suppress errors when widthing params since short-circuiting in
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// the conditional evaluation may mean these error can never occur. We
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// then make sure that short-circuiting is used by constifyParamsEdit.
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@ -3208,6 +3250,9 @@ class ParamVisitor final : public VNVisitor {
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iterateAndNextNull(forp->initsp());
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iterateAndNextNull(forp->condp());
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iterateAndNextNull(forp->incsp());
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// Cond/init/inc may reference deferred lparams whose Dot is still
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// pending; resolve them so widthing/constify can see Consts.
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m_processor.resolveDeferredDotsReachableFrom(forp, m_modp);
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V3Width::widthParamsEdit(forp); // Param typed widthing will NOT recurse the body
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// Outer wrapper around generate used to hold genvar, and to ensure genvar
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// doesn't conflict in V3LinkDot resolution with other genvars
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@ -3241,6 +3286,9 @@ class ParamVisitor final : public VNVisitor {
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AstNode* keepp = nullptr;
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iterateAndNextNull(nodep->exprp());
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V3Case::caseLint(nodep);
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// expr / case items may reference deferred lparams whose Dot is still
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// pending; resolve them so widthing/constify can see Consts.
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m_processor.resolveDeferredDotsReachableFrom(nodep, m_modp);
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V3Width::widthParamsEdit(nodep); // Param typed widthing will NOT recurse the
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// body, don't trigger errors yet.
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V3Const::constifyParamsEdit(nodep->exprp()); // exprp may change
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Edmund Lam
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--binary'])
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test.execute()
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test.passes()
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@ -0,0 +1,65 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Generate-for / generate-if / generate-case conditions that reference
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// a class-scope-resolved deferred localparam (e.g. inst::b). V3Param's
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// visit(AstGenIf/Block/Case) calls V3Width::widthParamsEdit /
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// constify on the cond/expr; the same transitive Dot-resolution used
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// for cell pins must be applied here so the deferred lparam folds.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Edmund Lam
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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// Cell whose presence is observable, used inside generate blocks
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// below to confirm each generate flavour elaborated the right way.
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module Tag #(
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parameter int ID
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) ();
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initial $write("Tag ID=%0d\n", ID);
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endmodule
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module t;
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virtual class C #(
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parameter int a
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);
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localparam int b = a;
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endclass
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typedef C#(3) c3;
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typedef C#(5) c5;
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// Deferred lparams
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localparam int b3 = c3::b;
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localparam int b5 = c5::b;
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// (1) Generate-for bound = deferred lparam
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for (genvar i = 0; i < b3; i++) begin : gf
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Tag #(100 + i) inst ();
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end
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// (2) Generate-if cond = deferred lparam
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if (b5 > b3) begin : gi_t
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Tag #(200) inst ();
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end else begin : gi_f
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Tag #(201) inst ();
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end
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// (3) Generate-case selector = deferred lparam
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case (b5)
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3: begin : gc Tag #(303) inst (); end
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5: begin : gc Tag #(305) inst (); end
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default: begin : gc Tag #(399) inst (); end
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endcase
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initial begin
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`checkh(b3, 32'd3);
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`checkh(b5, 32'd5);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Edmund Lam
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--binary'])
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test.execute()
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test.passes()
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@ -0,0 +1,66 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Interface-instance parameter pins whose value chains through a
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// class-scope-resolved localparam (typedef alias of a parameterized
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// class, e.g. inst::b). Same cell-deparam fix that handles module
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// instances must also handle interface instances and downstream
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// port-bound consumers.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Edmund Lam
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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interface SubIface #(
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parameter int IW
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) ();
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logic [IW-1:0] data;
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endinterface
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// Module that takes an interface port — must elaborate after the iface
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// cell pin is fully constified.
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module Consumer (
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SubIface si
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);
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endmodule
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module t;
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virtual class C #(
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parameter int a
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);
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localparam int b = a;
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endclass
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typedef C#(8) c8;
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typedef C#(13) c13;
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// Deferred lparams
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localparam int b8 = c8::b;
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localparam int b13 = c13::b;
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// Chained
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localparam int b8_alias = b8;
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// Iface pin = bare VarRef to deferred lparam
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SubIface #(b8) i_bare ();
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// Iface pin = chained VarRef
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SubIface #(b8_alias) i_chain ();
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// Iface pin = expression mixing deferred lparams
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SubIface #(b8 + b13) i_expr ();
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// Iface used as a module port — exercises the iface-cell-first path
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Consumer cons (.si(i_bare));
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initial begin
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`checkh(b8, 32'd8);
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`checkh(b13, 32'd13);
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`checkh(b8_alias, 32'd8);
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`checkh($bits(i_bare.data), 32'd8);
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`checkh($bits(i_chain.data), 32'd8);
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`checkh($bits(i_expr.data), 32'd21);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Edmund Lam
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--binary'])
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test.execute()
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test.passes()
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@ -0,0 +1,71 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Module-instance parameter pins whose value chains through a
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// class-scope-resolved localparam (typedef alias of a parameterized
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// class, e.g. inst::b). V3LinkDot defers the inst::b Dot until
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// post-V3Param; the cell deparam must follow VarRefs into any
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// deferred lparam reachable from the pin tree and resolve its Dots
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// inline so constify on the cell can fold.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Edmund Lam
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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module Sub #(
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parameter int WIDTH
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) ();
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endmodule
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// Two-level: outer module forwards its param to an inner cell, so the
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// deferred lparam value must flow through the cell-deparam chain.
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module SubL1 #(
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parameter int W
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) ();
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Sub #(W) inner ();
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endmodule
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module t;
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virtual class C #(
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parameter int a
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);
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localparam int b = a;
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endclass
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typedef C#(4) c4;
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typedef C#(5) c5;
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typedef C#(8) c8;
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// Deferred lparams (value contains class::member Dot)
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localparam int b4 = c4::b;
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localparam int b5 = c5::b;
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localparam int b8 = c8::b;
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// Chained: value references another deferred lparam
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localparam int c8_ref = b8;
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localparam int d8_ref = c8_ref + 1;
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// Pin is bare VarRef to a deferred lparam
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Sub #(b8) m_bare ();
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// Pin chains through multiple deferred lparams (b8 -> c8_ref -> d8_ref)
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Sub #(d8_ref) m_chain ();
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// Pin is an expression mixing two deferred lparams
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Sub #(b4 + b5) m_expr ();
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// Pin mixes a Dot and a deferred lparam in the same expression
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Sub #(c4::b + b5) m_mix ();
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// Two-level: outer module forwards param to inner cell
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SubL1 #(b8) m_l1 ();
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initial begin
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`checkh(b4, 32'd4);
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`checkh(b5, 32'd5);
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`checkh(b8, 32'd8);
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`checkh(c8_ref, 32'd8);
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`checkh(d8_ref, 32'd9);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
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#
|
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# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of either the GNU Lesser General Public License Version 3
|
||||
# or the Perl Artistic License Version 2.0.
|
||||
# SPDX-FileCopyrightText: 2026 Edmund Lam
|
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--binary'])
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test.execute()
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test.passes()
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@ -0,0 +1,60 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Typedefs and class type parameters that resolve through a
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// class-scope-resolved localparam (typedef alias of a parameterized
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// class, e.g. inst::b). Exercises three sub-cases:
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// - Deferred lparam used as a packed range bound in a typedef
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// - Deferred lparam used as a value argument to a parameterized class
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// - Class-scope-resolved typedef that itself depends on the param
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Edmund Lam
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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module t;
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virtual class C #(
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parameter int a
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);
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localparam int b = a;
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typedef logic [a-1:0] inner_t;
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// localparam derived from a typedef inside the same class —
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// resolveDotToTypedef must constify this when reached via CFG::width.
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localparam int width = $bits(inner_t);
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endclass
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typedef C#(8) c8;
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// Deferred lparam (direct Dot)
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localparam int b8 = c8::b;
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// (1) typedef range driven by a deferred lparam
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typedef logic [b8-1:0] data_t;
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data_t data_value;
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// (2) class type-arg uses a deferred lparam value
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typedef C#(b8) c_from_def;
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localparam int from_def_b = c_from_def::b;
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// (3) class-scope-resolved typedef computed via $bits(inner_t)
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localparam int via_bits = c8::width;
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// Wire whose range comes from a deferred lparam
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logic [b8-1:0] wide_bus;
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initial begin
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`checkh(b8, 32'd8);
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`checkh(from_def_b, 32'd8);
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`checkh(via_bits, 32'd8);
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data_value = '1;
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||||
`checkh(data_value, 8'hff);
|
||||
wide_bus = '1;
|
||||
`checkh(wide_bus, 8'hff);
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
Loading…
Reference in New Issue