Update test

Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>

test_regress/t/t_fork_write_after_timing.out

@@ -8,10 +8,10 @@ t4 start          -1
 t4 end           2
 t1 start           1
 t1 end           1
-t2 start           1
-t2 end           1
+t2 start          -1
+t2 end          -1
 t3 start           1
 t3 end           1
-t4 start           1
+t4 start           2
 t4 end           2
 *-* All Finished *-*

test_regress/t/t_fork_write_after_timing.v

@@ -4,7 +4,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t;
-  int x1, x2, x3, x4;
+  int x1, x2, x3, x4, x5, x6, x7;
 
   initial begin
     x1 = -1;
@@ -18,13 +18,20 @@ module t;
     t4(x4);
 
     #10 t1(x1);
-    t2(x1);
-    t3(x1);
-    t4(x1);
+    t2(x2);
+    t3(x3);
+    t4(x4);
+
+    if (x5 != 3) $stop;
+    if (x6 != 0) $stop;
+    if (x7 != 4) $stop;
 
     #5 $write("*-* All Finished *-*\n");
     $finish;
   end
+  always #1 t5(x5);
+  always #1 t6(x6);
+  always #1 t7(x7);
 
   task t1(output int x);
     $display("t1 start %d", x);
@@ -57,4 +64,19 @@ module t;
     join_none
     #2 $display("t4 end %d", x);
   endtask
+
+  task t5(output int x);
+    x <= #1 3;
+  endtask
+
+  task t6(inout int x);
+    x <= #1 4;
+  endtask
+
+  task static t7(inout int x);
+    int y = 0;
+    x <= #1 4;
+    #2 y = x;
+    if (y != 4) $stop;
+  endtask
 endmodule