luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix formatting 

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
This commit is contained in:
Krzysztof Bieganski 2025-12-23 15:35:58 +01:00
parent b685389ea4
commit 747befb3a0
1 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
test_regress/t/t_interface_virtual_cond.v
View File

@ -5,23 +5,23 @@
// SPDX-License-Identifier: CC0-1.0
interface Bus;
logic [15:0] data;
logic [15:0] data;
endinterface
module t;
Bus intf();
virtual Bus vif;
Bus intf();
virtual Bus vif;
function logic get_vif(inout virtual Bus vif);
vif = intf;
return 0;
endfunction
function logic get_vif(inout virtual Bus vif);
vif = intf;
return 0;
endfunction
initial begin
if (get_vif(vif));
while (get_vif(vif));
do ; while (get_vif(vif));
for (int i = 0; get_vif(vif); i++);
end
initial begin
if (get_vif(vif));
while (get_vif(vif));
do ; while (get_vif(vif));
for (int i = 0; get_vif(vif); i++);
end
endmodule