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Support for loop i++, ++i, i--, --i, bug175.

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Wilson Snyder 2009-11-10 16:40:07 -05:00
parent 376147911f
commit 736b9074c8
3 changed files with 34 additions and 0 deletions
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2
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@ -20,6 +20,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Support optional cell parenthesis, bug179. [by Byron Bradley]
**** Support for loop i++, ++i, i--, --i, bug175. [by Byron Bradley]
**** Fix Verilator core dump on wide integer divides, bug178. [Byron Bradley]
* Verilator 3.720 2009/10/26

4
src/verilog.y
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@ -1837,6 +1837,10 @@ for_stepE<nodep>: // IEEE: for_step + empty
for_step<nodep>: // IEEE: for_step
varRefBase '=' expr { $$ = new AstAssign($2,$1,$3); }
| yP_PLUSPLUS varRefBase { $$ = new AstAssign($1,$2,new AstAdd ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))) }
| yP_MINUSMINUS varRefBase { $$ = new AstAssign($1,$2,new AstSub ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))) }
| varRefBase yP_PLUSPLUS { $$ = new AstAssign($2,$1,new AstAdd ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))) }
| varRefBase yP_MINUSMINUS { $$ = new AstAssign($2,$1,new AstSub ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))) }
//UNSUP: List of steps
;

28
test_regress/t/t_for_loop.v
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@ -49,6 +49,34 @@ module t (/*AUTOARG*/
loops = loops + 1;
end
if (loops !== 100000) $stop;
// Test post-increment
loops = 0;
for (i=0; i<=16; i++) begin
loops = loops + 1;
end
if (i !== 17) $stop;
if (loops !== 17) $stop;
// Test pre-increment
loops = 0;
for (i=0; i<=16; ++i) begin
loops = loops + 1;
end
if (i !== 17) $stop;
if (loops !== 17) $stop;
// Test post-decrement
loops = 0;
for (i=16; i>=0; i--) begin
loops = loops + 1;
end
if (i !== -1) $stop;
if (loops !== 17) $stop;
// Test pre-decrement
loops = 0;
for (i=16; i>=0; --i) begin
loops = loops + 1;
end
if (i !== -1) $stop;
if (loops !== 17) $stop;
//
$write("*-* All Finished *-*\n");
$finish;