Tests: Add coverpoints test (#6118)

test_regress/driver.py

@@ -735,10 +735,19 @@ class VlTest:
         self.nc_define = 'NC'
         self.nc_flags = [
             "+licqueue", "+nowarn+LIBNOU", "+define+NC=1", "-q", "+assert", "+sv", "-c",
-            ("+access+r" if Args.trace else "")
+            "-xmlibdirname", (self.obj_dir + "/xcelium.d"), ("+access+r" if Args.trace else "")
         ]
         self.nc_flags2 = []  # Overridden in some sim files
-        self.nc_run_flags = ["+licqueue", "-q", "+assert", "+sv", "-R"]
+        self.nc_run_flags = [
+            "+licqueue",
+            "-q",
+            "+assert",
+            "+sv",
+            "-R",
+            "-covoverwrite",
+            "-xmlibdirname",
+            (self.obj_dir + "/xcelium.d"),
+        ]
         # ModelSim
         self.ms_define = 'MS'
         self.ms_flags = [

test_regress/t/t_covergroup_coverpoints_unsup.out

@@ -0,0 +1,29 @@
+%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:21:5: Ignoring unsupported: covergroup
+   21 |     covergroup cg @(posedge clk);
+      |     ^~~~~~~~~~
+                   ... For warning description see https://verilator.org/warn/COVERIGN?v=latest
+                   ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message.
+%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:21:19: Ignoring unsupported: coverage clocking event
+   21 |     covergroup cg @(posedge clk);
+      |                   ^
+%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:22:9: Ignoring unsupported: coverpoint
+   22 |         coverpoint a;
+      |         ^~~~~~~~~~
+%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:24:31: Ignoring unsupported: cover bin specification
+   24 |             bins the_bins [5] = { [0:20] };
+      |                               ^
+%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:23:9: Ignoring unsupported: coverpoint
+   23 |         coverpoint b {
+      |         ^~~~~~~~~~
+%Error: t/t_covergroup_coverpoints_unsup.v:35:48: Member 'a' not found in class 'cg'
+                                                : ... note: In instance 't'
+   35 |             $display("coverage a = %f", the_cg.a.get_inst_coverage());
+      |                                                ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:35:50: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic''
+                                                            : ... note: In instance 't'
+   35 |             $display("coverage a = %f", the_cg.a.get_inst_coverage());
+      |                                                  ^~~~~~~~~~~~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt
+%Error: Command Failed

test_regress/t/t_covergroup_coverpoints_unsup.py

@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+if test.vlt_all:
+    test.lint(fails=True, expect_filename=test.golden_filename)
+else:
+    test.compile(nc_flags2=["-coverage", "functional"])
+    test.execute()
+
+test.passes()

test_regress/t/t_covergroup_coverpoints_unsup.v

@@ -0,0 +1,43 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+    // Inputs
+    clk
+    );
+
+    input clk;
+    logic [3:0]  a;
+    int   b;
+    int cyc = 0;
+
+    always @(posedge clk) begin
+        cyc <= cyc + 1;
+    end
+
+    covergroup cg @(posedge clk);
+        coverpoint a;
+        coverpoint b {
+            bins the_bins [5] = { [0:20] };
+        }
+    endgroup
+
+    cg the_cg = new;
+
+    assign a = cyc[3:0];
+    assign b = cyc;
+
+    always @(posedge clk) begin
+        if (cyc == 14) begin
+            $display("coverage a = %f", the_cg.a.get_inst_coverage());
+            $display("coverage b = %f", the_cg.b.get_inst_coverage());
+            if (the_cg.a.get_inst_coverage() != 15/16.0) $stop();
+            if (the_cg.b.get_inst_coverage() != 4/5.0) $stop();
+            $write("*-* All Finished *-*\n");
+            $finish;
+        end
+    end
+endmodule