Fix linking suppressing duplicate var and block name errors

src/V3Link.cpp

@@ -173,7 +173,7 @@ private:
 	    foundp = nodep;
 	} else if (nodep==foundp) {  // Already inserted.
 	    // Good.
-	} else if ((nodep->castBegin() || foundp->castBegin())
+	} else if ((nodep->castBegin() && foundp->castBegin())
 		   && m_inGenerate) {
 	    // Begin: ... blocks often replicate under genif/genfor, so simply suppress duplicate checks
 	    // See t_gen_forif.v for an example.

test_regress/t/t_lint_block_redecl_bad.pl

@@ -0,0 +1,25 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug485, false begin due to WHILE conversion blocks duplicate name detection");
+
+compile (
+    v_flags2 => ["--lint-only"],
+    fails=>1,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    expect=>
+'%Warning: duplicate...
+%Error: Exiting due to.*',
+    );
+
+ok(1);
+1;

test_regress/t/t_lint_block_redecl_bad.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+//bug485, but see t_gen_forif.v for an OK example.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   always_comb begin
+      integer i;
+
+      for(i=0; i<10; i++ ) begin: COMB
+      end
+
+      for(i=0; i<9; i++ ) begin: COMB
+      end
+   end
+endmodule