Fix definitions in main file.v, referenced in library. [Stefan Thiede]

git-svn-id: file://localhost/svn/verilator/trunk/verilator@999 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -12,6 +12,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix assignments to inputs inside functions/tasks.  [Patricio Kaplan]
 
+**** Fix definitions in main file.v, referenced in library.  [Stefan Thiede]
+
 * Verilator 3.658 2008/02/25
 
 **** Fix unistd compile error in 3.657.  [Patricio Kaplan, Jonathan Kimmitt]

Makefile.in

@@ -141,6 +141,7 @@ msg_test:
 	@echo "Type 'make test' to test."
 	@echo
 
+.PHONY:test
 ifeq ($(VERILATOR_AUTHOR_SITE),1)	# Local... Else don't burden users
 test: test_vcs test_c test_sc test_sp test_verilated test_regress
 else

src/Verilator.cpp

@@ -90,14 +90,17 @@ V3Global v3Global;
 
 void V3Global::readFiles() {
     V3Read reader (m_rootp);
+    // Read top module
+    reader.readFile(new FileLine("CommandLine",0), opt.top(), false);
+
     // Read libraries
+    // To be compatible with other simulators,
+    // this needs to be done after the top file is read
     for (V3StringSet::iterator it = v3Global.opt.libraryFiles().begin();
 	 it != v3Global.opt.libraryFiles().end(); ++it) {
 	string filename = *it;
 	reader.readFile(new FileLine("CommandLine",0), filename, true);
     }
-    // Read top module
-    reader.readFile(new FileLine("CommandLine",0), opt.top(), false);
     V3Error::abortIfErrors();
 }
 

test_regress/Makefile

@@ -39,6 +39,7 @@ endif
 
 ######################################################################
 
+.PHONY: test
 test:
 	$(PERL) driver.pl $(DRIVER_FLAGS) $(PRODUCTS)
 

test_regress/t/t_pp_lib.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => ['-v', 't/t_pp_lib_library.v'],
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
+

test_regress/t/t_pp_lib.v

@@ -0,0 +1,11 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+`include "t_pp_lib_inc.v"
+module t();
+   wire [`WIDTH-1:0] a;
+   library_cell n1(a);
+endmodule

test_regress/t/t_pp_lib_inc.v

@@ -0,0 +1,7 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+`define WIDTH 10

test_regress/t/t_pp_lib_library.v

@@ -0,0 +1,13 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module library_cell(a);
+   input [`WIDTH-1:0] a;
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule