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Support strength on buf/not

This commit is contained in:
Wilson Snyder 2026-05-31 08:54:29 -04:00
parent 5def7c2b5d
commit 72ed55b180
5 changed files with 65 additions and 36 deletions
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16
src/verilog.y
View File

@ -66,12 +66,6 @@ static void STRENGTH_LIST(AstNode* listp, AstStrengthSpec* specp) {
assignp->strengthSpecp(specp->backp() ? specp->cloneTree(false) : specp);
}
}
static void STRENGTHUNSUP(AstStrengthSpec* nodep) {
if (!nodep) return;
BBUNSUP((nodep->fileline()), "Unsupported: Strength specifier on this gate type");
nodep->deleteTree();
}
//======================================================================
// Statics (for here only)
@ -5613,12 +5607,12 @@ let_port_item<varp>: // IEEE: let_port_Item
// Gate declarations
gateDecl<nodep>:
yBUF driveStrengthE delay_controlE gateBufList ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($4, $3); }
| yBUFIF0 driveStrengthE delay_controlE gateBufif0List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($4, $3); }
| yBUFIF1 driveStrengthE delay_controlE gateBufif1List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($4, $3); }
yBUF driveStrengthE delay_controlE gateBufList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yBUFIF0 driveStrengthE delay_controlE gateBufif0List ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yBUFIF1 driveStrengthE delay_controlE gateBufif1List ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yNOT driveStrengthE delay_controlE gateNotList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yNOTIF0 driveStrengthE delay_controlE gateNotif0List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($4, $3); }
| yNOTIF1 driveStrengthE delay_controlE gateNotif1List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($4, $3); }
| yNOTIF0 driveStrengthE delay_controlE gateNotif0List ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yNOTIF1 driveStrengthE delay_controlE gateNotif1List ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yAND driveStrengthE delay_controlE gateAndList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yNAND driveStrengthE delay_controlE gateNandList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yOR driveStrengthE delay_controlE gateOrList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }

8
test_regress/t/t_strength_bufif1.py → test_regress/t/t_strength_buf_not.py
View File

@ -4,13 +4,15 @@
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
test.scenarios('simulator')
test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
test.compile(verilator_flags2=['--binary'])
test.execute()
test.passes()

55
test_regress/t/t_strength_buf_not.v Normal file
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@ -0,0 +1,55 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
// Based on iverilog/ivtest/ivltests/br918c.v by Cary R
module driver (
inout wire b0,
inout wire b1,
inout wire b2,
inout wire b3
);
reg [3:0] v;
buf (strong0, pull1) u_buf0 (b0, v[0]);
buf (strong0, pull1) u_buf1 (b1, v[1]);
not (strong0, pull1) u_not2 (b2, v[2]);
not (strong0, pull1) u_not3 (b3, v[3]);
initial v = 4'b1010;
endmodule
module t (input clk);
wire [3:0] bus;
pullup u_pu0 (bus[0]);
pullup u_pu1 (bus[1]);
pullup u_pu2 (bus[2]);
pullup u_pu3 (bus[3]);
driver u_driver (
.b0(bus[0]),
.b1(bus[1]),
.b2(bus[2]),
.b3(bus[3])
);
initial begin
#1;
`checkb(bus, 4'b0110);
$finish;
end
endmodule

5
test_regress/t/t_strength_bufif1.out
View File

@ -1,5 +0,0 @@
%Error-UNSUPPORTED: t/t_strength_bufif1.v:9:10: Unsupported: Strength specifier on this gate type
9 | bufif1 (strong0, strong1) (a, 1'b1, 1'b1);
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

17
test_regress/t/t_strength_bufif1.v
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@ -1,17 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
module t;
wire a;
bufif1 (strong0, strong1) (a, 1'b1, 1'b1);
always begin
if (a) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule