Fix incorrect nested interface-class error (#6549).

Changes

@@ -98,6 +98,7 @@ Verilator 5.041 devel
 * Fix DFG circular driver tracing with partial assignments. [Geza Lore]
 * Fix passing typedef value as parameter (#6543) (#6547). [Igor Zaworski, Antmicro Ltd.]
 * Fix indent error on quoted strings (#6544).
+* Fix incorrect nested interface-class error (#6549). [Matthew Ballance]
 
 
 Verilator 5.040 2025-08-30

src/V3LinkDot.cpp

@@ -4774,11 +4774,6 @@ class LinkDotResolveVisitor final : public VNVisitor {
         LINKDOT_VISIT_START();
         UINFO(5, indent() << "visit " << nodep);
         checkNoDot(nodep);
-        AstClass* const topclassp = VN_CAST(m_modp, Class);
-        if (nodep->isInterfaceClass() && topclassp && topclassp->isInterfaceClass()) {
-            nodep->v3error("Interface class shall not be nested within another interface class."
-                           " (IEEE 1800-2023 8.26)");
-        }
         VL_RESTORER(m_curSymp);
         VL_RESTORER(m_modSymp);
         VL_RESTORER(m_modp);

src/V3LinkParse.cpp

@@ -622,6 +622,11 @@ class LinkParseVisitor final : public VNVisitor {
     void visit(AstNodeModule* nodep) override {
         V3Control::applyModule(nodep);
         ++m_statModules;
+        if (VN_IS(nodep, Class) && VN_CAST(nodep, Class)->isInterfaceClass()
+            && VN_IS(m_modp, Class) && VN_CAST(m_modp, Class)->isInterfaceClass()) {
+            nodep->v3error("Interface class shall not be nested within another interface class."
+                           " (IEEE 1800-2023 8.26)");
+        }
 
         VL_RESTORER(m_modp);
         VL_RESTORER(m_anonUdpId);

test_regress/t/t_implements_not_nested.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_implements_not_nested.v

@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+package ipkg;
+  typedef interface class iclass;
+
+  interface class iclass;
+    pure virtual function void doit();
+  endclass
+endpackage
+
+package epkg;
+  interface class cclass2 extends ipkg::iclass;
+    pure virtual function void doit2();
+  endclass
+
+  class cclass implements cclass2;
+    virtual function void doit();
+      $display("doit");
+    endfunction
+    virtual function void doit2();
+      $display("doit2");
+    endfunction
+  endclass
+endpackage
+
+module top;
+  import epkg::*;
+
+  initial begin
+    automatic cclass c = new();
+    c.doit();
+    $finish;
+  end
+endmodule