Commentary: spelling

docs/spelling.txt

@@ -589,7 +589,9 @@ combinational
 combinatorial
 commandArgsPlusMatch
 compilable
+computable
 concat
+concatenatable
 concats
 conf
 config
@@ -629,6 +631,7 @@ defparam
 demangling
 dep
 deparametrized
+deque
 der
 dereference
 dereferenced
@@ -642,6 +645,7 @@ dev
 devcontainer
 devel
 dir
+disambiguates
 displayb
 distcc
 doxygen
@@ -670,6 +674,7 @@ elab
 eliasphanna
 elike
 elsif
+enablement
 endcase
 endcelldefine
 endclass
@@ -975,6 +980,8 @@ realtime
 realtobits
 recoding
 recrem
+recurse
+recurses
 redeclaring
 regs
 reloop

include/verilated_trace_imp.h

@@ -905,7 +905,7 @@ VerilatedTraceOffloadBuffer<VL_BUF_T>::VerilatedTraceOffloadBuffer(VL_SUB_T& own
         using This = VerilatedTraceBuffer<VL_BUF_T>*;
         // Tack on the buffer address
         static_assert(2 * sizeof(uint32_t) >= sizeof(This),
-                      "This should be enough on all plafrorms");
+                      "This should be enough on all platforms");
         *m_offloadBufferWritep++ = VerilatedTraceOffloadCommand::TRACE_BUFFER;
         *reinterpret_cast<This*>(m_offloadBufferWritep) = static_cast<This>(this);
         m_offloadBufferWritep += 2;

include/verilated_vcd_c.cpp

@@ -178,7 +178,7 @@ void VerilatedVcd::openNextImp(bool incFilename) {
         }
     }
     m_isOpen = true;
-    constDump(true);  // First dump must containt the const signals
+    constDump(true);  // First dump must contain the const signals
     fullDump(true);  // First dump must be full
     m_wroteBytes = 0;
 }

include/verilated_vpi.cpp

@@ -3069,7 +3069,7 @@ void vl_get_value_array_rawvals(unsigned index, unsigned num, const unsigned siz
                                 const unsigned packedSize, const bool leftIsLow,
                                 const bool fourState, const T* src, PLI_BYTE8* dst) {
     static_assert(std::is_unsigned<T>::value,
-                  "type T is not unsigned");  //ensure loigcal right shift
+                  "type T is not unsigned");  //ensure logical right shift
     const unsigned element_size_bytes VL_BYTES_I(packedSize);
     const unsigned element_size_repr = (element_size_bytes + sizeof(T) - 1) / sizeof(T);
     size_t dst_index = 0;

src/V3AstNodeExpr.h

@@ -832,7 +832,7 @@ public:
     bool rhsIsValue() const { return m_rhsIsValue; }
 };
 class AstConsPackMember final : public AstNodeExpr {
-    // Construct a packed array single emement [member1: value1]
+    // Construct a packed array single element [member1: value1]
     // Don't need the member we are constructing, as the dtypep can get us to it
     // @astgen op2 := rhsp : AstNodeExpr
 public:

src/V3AstNodeOther.h

@@ -290,7 +290,7 @@ class AstNodeModule VL_NOT_FINAL : public AstNode {
     bool m_hasGParam : 1;  // Has global parameter (for link)
     bool m_hasParameterList : 1;  // Has #() for parameter declaration
     bool m_hierBlock : 1;  // Hierarchical Block marked by HIER_BLOCK pragma
-    bool m_hierParams : 1;  // Block containing params for parametrized hier blocks
+    bool m_hierParams : 1;  // Block containing params for parameterized hier blocks
     bool m_internal : 1;  // Internally created
     bool m_recursive : 1;  // Recursive module
     bool m_recursiveClone : 1;  // If recursive, what module it clones, otherwise nullptr

src/V3Control.cpp

@@ -494,7 +494,7 @@ public:
     }
 
     bool getScopeTraceOn(const string& scope) {
-        // Apply in the order the user provided them, so they can choose on/off preferencing
+        // Apply in the order the user provided them, so they can choose on/off preferences
         int maxLevel = 1;
         for (const auto& ch : scope) {
             if (ch == '.') ++maxLevel;

src/V3Delayed.cpp

@@ -19,7 +19,7 @@
 // For the Pre/Post scheduling semantics, see V3OrderGraph.
 //
 // There are several "Schemes" we can choose from for implementing a
-// non-blocking assignment (NBA), repserented by an AstAssignDly.
+// non-blocking assignment (NBA), represented by an AstAssignDly.
 //
 // It is assumed and required in this pass that each NBA updates at
 // most one variable. Earlier passes should have ensured this.
@@ -442,7 +442,7 @@ class DelayedVisitor final : public VNVisitor {
         // Check for mixed usage (this also warns if not OK)
         if (checkMixedUsage(vscp, isIntegralOrPacked)) {
             // If it's a variable updated by both blocking and non-blocking
-            // asignments, use the ShadowVarMasked schem if masked update is
+            // assignments, use the ShadowVarMasked schem if masked update is
             // possible. This can handle blocking and non-blocking updates to
             // inpdendent parts correctly at run-time, and always works, even
             // in loops or other dynamic context.
@@ -1122,7 +1122,7 @@ class DelayedVisitor final : public VNVisitor {
 
         // There were some timing domains involved in the process. Add all of them as sensitivities
         // of all NBA targets in this process. Note this is a bit of a sledgehammer, we should only
-        // need those that directly preceed the NBA in control flow, but that is hard to compute,
+        // need those that directly precede the NBA in control flow, but that is hard to compute,
         // so we will hammer away.
 
         // First gather all senItems

src/V3DfgSynthesize.cpp

@@ -862,7 +862,7 @@ class AstToDfgSynthesize final {
     }
 
     // If any written variables are forced or otherwise udpated from outside,
-    // we generally cannot synthesie the construct, as we will likely need to
+    // we generally cannot synthesize the construct, as we will likely need to
     // introduce intermediate values that would not be updated.
     static bool hasExternallyWrittenVariable(DfgLogic& vtx) {
         return vtx.findSink<DfgVertex>([](const DfgVertex& sink) -> bool {
@@ -896,7 +896,7 @@ class AstToDfgSynthesize final {
         UASSERT_OBJ(thenVarp == elseVarp, varp, "Attempting to join unrelated variables");
 
         // If both bindings are the the same (variable not updated through either path),
-        // then there is nothing to do, canuse the same binding
+        // then there is nothing to do, can use the same binding
         if (thenp == elsep) return thenp;
 
         // We can't join the input variable just yet, so bail
@@ -1344,7 +1344,7 @@ class AstToDfgSynthesize final {
         return true;
     }
 
-    // Assign path perdicates to the outgoing control flow edges of the given block
+    // Assign path predicates to the outgoing control flow edges of the given block
     void assignPathPredicates(const CfgBlock& bb) {
         // Nothing to do for the exit block
         if (bb.isExit()) return;
@@ -1398,7 +1398,7 @@ class AstToDfgSynthesize final {
         // It's possible we think a variable is written by the DfgLogic when
         // it actauly isn't, e.g.: '{a[0], b[0]}[1] = ...' does not write 'b'.
         // These LHS forms can happen after some earlier tranforms. We
-        // should just run V3Const on them earleir, but we will do belt and
+        // should just run V3Const on them earlier, but we will do belt and
         // braces and check here too. We can't touch any output variables if so.
         const bool missing = m_logicp->findSink<DfgVertex>([&](const DfgVertex& sink) -> bool {
             const DfgUnresolved* const unresolvedp = sink.as<DfgUnresolved>();

src/V3FuncOpt.cpp

@@ -280,7 +280,7 @@ class FuncOptVisitor final : public VNVisitor {
     // VISIT
     void visit(AstNodeAssign* nodep) override {
         // TODO: Only thing remaining inside functions should be AstAssign (that is, an actual
-        //       assignment statemant), but we stil use AstAssignW, AstAssignDly, and all, fix.
+        //       assignment statement), but we stil use AstAssignW, AstAssignDly, and all, fix.
         iterateChildren(nodep);
 
         if (v3Global.opt.fFuncSplitCat()) {

src/V3Gate.cpp

@@ -874,8 +874,8 @@ class GateInline final {
                     // (driver is same as sink), however, okVisitor rejects a circular driver
                     // and we would not reach here if the driver logic was actually circular.
                     // The reason we end up here is because during graph building, the driver
-                    // was ciruclar, however, after committing some substituions to it, it
+                    // was circular, however, after committing some substitutions to it, it
-                    // has become non-circualr due to V3Const being applied inside
+                    // has become non-circular due to V3Const being applied inside
                     // 'commitSubstitutions'. We will trust GateOkVisitor telling the truth
                     // that the logic is not actually circular, meaning this edge is not
                     // actually needed, can just delete it and move on.

src/V3HierBlock.cpp

@@ -40,7 +40,7 @@
 //    that are marked with /*verilator hier_block*/ metacomment in Verilator run a).
 // 2) If module type parameters are present, V3Control marks hier param modules
 // (marked with hier_params verilator config pragma) as modp->hierParams(true).
-// This is done in run b), de-parametrized modules are mapped with their params one-to-one.
+// This is done in run b), de-parameterized modules are mapped with their params one-to-one.
 // 3) AstModule with HIER_BLOCK pragma is marked modp->hierBlock(true)
 //    in V3LinkResolve.cpp during run a).
 // 4) In V3LinkCells.cpp, the following things are done during run b) and c).
@@ -56,8 +56,8 @@
 // 5) In V3LinkDot.cpp,
 //    5-1) Dotted access across hierarchical block boundary is checked. Currently hierarchical
 //    block references are not supported.
-//    5-2) If present, parameters in hier params module replace parameter values of de-parametrized
+//    5-2) If present, parameters in hier params module replace parameter values of
-//    module in run b).
+//    de-parameterized module in run b).
 // 6) In V3Dead.cpp, some parameters of parameterized modules are protected not to be deleted even
 //    if the parameter is not referred. This protection is necessary to match step 6) below.
 // 7) In V3Param.cpp, use --lib-create wrapper of the parameterized module made in b) and c).
@@ -82,7 +82,7 @@
 //      filename    :Name of a hierarchical parameters file
 //
 //      Added in a), used for b).
-//      Each de-parametrized module version has exactly one hier params file specified.
+//      Each de-parameterized module version has exactly one hier params file specified.
 
 #include "V3PchAstNoMT.h"  // VL_MT_DISABLED_CODE_UNIT
 

src/V3Inline.cpp

@@ -431,7 +431,7 @@ namespace ModuleInliner {
 // the instance and the port variable, or simply inline the pin expression
 // in place of the port variable. We will prefer to do the later whenever
 // possible (and sometimes required). When inlining, we need to create an
-// alias for the inined variable, in order to resovle hierarchical refrences
+// alias for the inlined variable, in order to resovle hierarchical references
 // against it later in V3Scope (and also for tracing, which is inserted
 //later). Returns ture iff the given port variable should be inlined,
 // and false if a continuous assignment should be used.
@@ -445,7 +445,7 @@ bool inlinePort(AstVar* nodep) {
     if (nodep->isForced()) return false;
 
     // Note: For singls marked 'public' (and not 'public_flat') inlining
-    // of their contaning modules is disabled so they wont reach here.
+    // of their containing modules is disabled so they wont reach here.
 
     // TODO: For now, writable public signals inside the cell cannot be
     // eliminated as they are entered into the VerilatedScope, and
@@ -618,7 +618,7 @@ void process(AstNetlist* netlistp, ModuleStateUser1Allocator& moduleStates) {
     while (AstNodeModule* const modp = VN_CAST(nodep, NodeModule)) {
         nodep = nodep->backp();
 
-        // Consider each cell inside the current module for inling
+        // Consider each cell inside the current module for inlining
         for (AstCell* const cellp : moduleStates(modp).m_childCells) {
             ModuleState& childState = moduleStates(cellp->modp());
             if (!childState.m_inlined) continue;

src/V3LifePost.cpp

@@ -199,7 +199,7 @@ class LifePostDlyVisitor final : public VNVisitorConst {
 
         // We need to be able to pick up the first write of each variable.
         // V3Order serializes all writes, and we trace AstExecGraph in
-        // dependency order, so the first one we encouner during tracing should
+        // dependency order, so the first one we encounter during tracing should
         // always be the one. It's somewhat expensive to assert so only with debugCheck().
         if (v3Global.opt.debugCheck()) {
             for (auto& pair : m_writes) {

src/V3LinkDot.cpp

@@ -2678,7 +2678,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
     }
     void classExtendImport(AstClass* nodep) {
         // A class reference might be to a class that is later in Ast due to
-        // e.g. parmaeterization or referring to a "class (type T) extends T"
+        // e.g. parameterization or referring to a "class (type T) extends T"
         // Resolve it so later Class:: references into its base classes work
         symIterateNull(nodep, m_statep->getNodeSym(nodep));
     }

src/V3Number.cpp

@@ -1835,7 +1835,7 @@ V3Number& V3Number::opShiftR(const V3Number& lhs, const V3Number& rhs) {
 }
 
 V3Number& V3Number::opShiftRS(const V3Number& lhs, const V3Number& rhs, uint32_t lbits) {
-    // Correct number of zero bits/width matters (hance lbits passed)
+    // Correct number of zero bits/width matters (hence lbits passed)
     // L(lhs) bit return
     // The spec says a unsigned >>> still acts as a normal >>.
     // We presume it is signed; as that's V3Width's job to convert to opShiftR

src/V3Param.cpp

@@ -548,7 +548,7 @@ class ParamProcessor final {
             // constp can be nullptr
 
             if (const AstConst* const p = VN_CAST(nodep, Const)) {
-                // Treat modules parametrized with the same values but with different type as the
+                // Treat modules parameterized with the same values but with different type as the
                 // same.
                 longname += p->num().ascii(false);
             } else if (nodep) {

src/V3Timing.cpp

@@ -685,7 +685,7 @@ class TimingControlVisitor final : public VNVisitor {
     }
     // Move `insertBeforep` into `AstCLocalScope` if necessary to avoid jumping over
     // a variable initialization that whould be inserted before `insertBeforep`. All
-    // access to this variable shoule be contained within returned `AstCLocalScope`.
+    // access to this variable should be contained within returned `AstCLocalScope`.
     AstCLocalScope* addCLocalScope(FileLine* const flp, AstNode* const insertBeforep) const {
         if (!insertBeforep || !m_underJumpBlock) return nullptr;
         VNRelinker handle;

test_regress/t/t_clk_inp_init.v

@@ -1,6 +1,6 @@
 // DESCRIPTION: Verilator: Check initialisation of cloned clock variables
 //
-// This tests issue #1327 (Strange initialisation behaviour with
+// This tests issue #1327 (Strange initialization behavior with
 // "VinpClk" cloned clock variables)
 //
 // This file ONLY is placed into the Public Domain, for any use,

test_regress/t/t_interface_import_param.v

@@ -1,6 +1,6 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// A test that a package import declaration can preceed a parameter port list
+// A test that a package import declaration can precede a parameter port list
 // in an interface declaration. See IEEE 1800-2023 25.3.
 //
 // This file ONLY is placed into the Public Domain, for any use,

test_regress/t/t_lint_removed_unused_loop_bad.v

@@ -62,7 +62,7 @@ module unused(input clk);
    end
 endmodule
 
-// no warning for loops under parametrized module
+// no warning for loops under parameterized module
 module parametrized_initial #(parameter REPETITIONS = 0);
    int prints_while = 0;
    int prints_do_while = 0;
@@ -228,21 +228,21 @@ module if_with_param;
 
    initial begin
       if (ZERO_PARAM) begin
-         // loop under false parametrized if - no warning
+         // loop under false parameterized if - no warning
          int prints = 0;
          while(prints < 5) begin
             prints++;
          end
          $write("Prints %d\n", prints);
       end else if (!ONE_PARAM) begin
-         // loop under false parametrized if - no warning
+         // loop under false parameterized if - no warning
          int prints = 0;
          while(prints < 5) begin
             prints++;
          end
          $write("Prints %d\n", prints);
       end else begin
-         // loop under true parametrized if - no warning
+         // loop under true parameterized if - no warning
          int prints = 0;
          while(prints < 5) begin
             prints++;