Tests: Check and fix ascending uvm_hdl_read/deposit

This commit is contained in:
Wilson Snyder 2026-01-11 05:08:57 -05:00
parent 54b130e43f
commit 703c82cb3d
9 changed files with 81 additions and 8 deletions

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@ -44,6 +44,11 @@ module t;
logic not_exposed; logic not_exposed;
logic exposed_not_forceable; logic exposed_not_forceable;
logic [83:4] wide_dec /* verilator public*/;
// verilator lint_off ASCRANGE
logic [4:83] wide_asc /* verilator public*/;
// verilator lint_on ASCRANGE
uvm_hdl_data_t lval; uvm_hdl_data_t lval;
initial begin initial begin
@ -138,6 +143,30 @@ module t;
`checkh(i, 1); `checkh(i, 1);
`checkh(exposed, 32'ha12d); `checkh(exposed, 32'ha12d);
$display("= uvm_hdl_read/deposit wide decending");
wide_dec = 80'h1234_56789abc_dcba8765;
lval = '0; // Upper bits not cleared by uvm_hdl_read
i = uvm_hdl_read("t.wide_dec[79:64]", lval);
`checkh(i, 1);
`checkh(lval[15:0], wide_dec[79:64]);
lval = 1024'hffe;
i = uvm_hdl_deposit("t.wide_dec[79:64]", lval);
`checkh(i, 1);
// .vvv_v......._........
`checkh(wide_dec, 80'h10ff_e6789abc_dcba8765);
$display("= uvm_hdl_read/deposit wide ascending");
wide_asc = 80'h1234_56789abc_dcba8765;
lval = '0; // Upper bits not cleared by uvm_hdl_read
i = uvm_hdl_read("t.wide_asc[64:79]", lval);
`checkh(i, 1);
`checkh(lval[15:0], wide_asc[64:79]);
lval = 1024'hffe;
i = uvm_hdl_deposit("t.wide_asc[64:79]", lval);
`checkh(i, 1);
// ...._........_...vvvv.
`checkh(wide_asc, 80'h1234_56789abc_dcb0ffe5);
$display("= uvm_hdl_deposit bad ranges"); $display("= uvm_hdl_deposit bad ranges");
$display("===\nUVM Report expected on next line:"); $display("===\nUVM Report expected on next line:");
i = uvm_hdl_deposit("t.exposed[10:3]", lval); i = uvm_hdl_deposit("t.exposed[10:3]", lval);

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@ -1,4 +1,4 @@
UVM Report t/t_uvm_dpi.v:54: id message UVM Report t/t_uvm_dpi.v:59: id message
uvm_dpi_get_tool_name_c() = Verilator uvm_dpi_get_tool_name_c() = Verilator
= uvm_re = uvm_re
= uvm_hdl_check_path = uvm_hdl_check_path
@ -8,6 +8,8 @@ uvm_dpi_get_tool_name_c() = Verilator
= uvm_hdl_deposit single bit = uvm_hdl_deposit single bit
= uvm_hdl_read multi-bit = uvm_hdl_read multi-bit
= uvm_hdl_deposit multi-bit = uvm_hdl_deposit multi-bit
= uvm_hdl_read/deposit wide decending
= uvm_hdl_read/deposit wide ascending
= uvm_hdl_deposit bad ranges = uvm_hdl_deposit bad ranges
=== ===
UVM Report expected on next line: UVM Report expected on next line:

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@ -1,4 +1,4 @@
UVM Report t/t_uvm_dpi.v:54: id message UVM Report t/t_uvm_dpi.v:59: id message
uvm_dpi_get_tool_name_c() = Verilator uvm_dpi_get_tool_name_c() = Verilator
= uvm_re = uvm_re
= uvm_hdl_check_path = uvm_hdl_check_path
@ -8,6 +8,8 @@ uvm_dpi_get_tool_name_c() = Verilator
= uvm_hdl_deposit single bit = uvm_hdl_deposit single bit
= uvm_hdl_read multi-bit = uvm_hdl_read multi-bit
= uvm_hdl_deposit multi-bit = uvm_hdl_deposit multi-bit
= uvm_hdl_read/deposit wide decending
= uvm_hdl_read/deposit wide ascending
= uvm_hdl_deposit bad ranges = uvm_hdl_deposit bad ranges
=== ===
UVM Report expected on next line: UVM Report expected on next line:

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@ -475,6 +475,28 @@ int _mon_check_var() {
return errors; return errors;
} }
int _mon_check_rev() {
t_vpi_value value;
TestVpiHandle vh9 = VPI_HANDLE("rev");
CHECK_RESULT_NZ(vh9);
value.format = vpiIntVal;
{
TestVpiHandle vh10 = vpi_handle(vpiLeftRange, vh9);
CHECK_RESULT_NZ(vh10);
vpi_get_value(vh10, &value);
TEST_CHECK_EQ(value.value.integer, 8);
TestVpiHandle vh11 = vpi_handle(vpiRightRange, vh9);
CHECK_RESULT_NZ(vh11);
vpi_get_value(vh11, &value);
TEST_CHECK_EQ(value.value.integer, 19);
value.format = vpiVectorVal;
vpi_get_value(vh9, &value);
CHECK_RESULT(value.value.vector[0].aval, 0xabc);
}
return errors;
}
int _mon_check_varlist() { int _mon_check_varlist() {
const char* p; const char* p;
@ -789,10 +811,14 @@ int _mon_check_delayed() {
CHECK_RESULT_NZ(vpi_chk_error(nullptr)); CHECK_RESULT_NZ(vpi_chk_error(nullptr));
// This format throws an error now // This format throws an error now
#ifdef VERILATOR
Verilated::fatalOnVpiError(false); Verilated::fatalOnVpiError(false);
#endif
v.format = vpiObjTypeVal; v.format = vpiObjTypeVal;
vpi_put_value(vh, &v, &t, vpiInertialDelay); vpi_put_value(vh, &v, &t, vpiInertialDelay);
#ifdef VERILATOR
Verilated::fatalOnVpiError(true); Verilated::fatalOnVpiError(true);
#endif
return 0; return 0;
} }
@ -993,6 +1019,7 @@ extern "C" int mon_check() {
if (int status = _mon_check_callbacks()) return status; if (int status = _mon_check_callbacks()) return status;
if (int status = _mon_check_value_callbacks()) return status; if (int status = _mon_check_value_callbacks()) return status;
if (int status = _mon_check_var()) return status; if (int status = _mon_check_var()) return status;
if (int status = _mon_check_rev()) return status;
if (int status = _mon_check_varlist()) return status; if (int status = _mon_check_varlist()) return status;
if (int status = _mon_check_var_long_name()) return status; if (int status = _mon_check_var_long_name()) return status;
// Ports are not public_flat_rw in t_vpi_var // Ports are not public_flat_rw in t_vpi_var

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@ -37,6 +37,7 @@ extern "C" int mon_check();
// verilator lint_off ASCRANGE // verilator lint_off ASCRANGE
reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */; reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */;
reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */;
// verilator lint_on ASCRANGE // verilator lint_on ASCRANGE
reg [31:0] count /*verilator public_flat */; reg [31:0] count /*verilator public_flat */;
@ -89,6 +90,8 @@ extern "C" int mon_check();
real1 = 1.0; real1 = 1.0;
str1 = "hello"; str1 = "hello";
rev = 12'habc;
`ifdef VERILATOR `ifdef VERILATOR
status = $c32("mon_check()"); status = $c32("mon_check()");
`endif `endif

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@ -47,6 +47,7 @@ extern "C" int mon_check();
reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND;
// verilator lint_off ASCRANGE // verilator lint_off ASCRANGE
reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk)*/; reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk)*/;
reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */;
/*verilator public_off*/ /*verilator public_off*/
reg invisible1; reg invisible1;
// verilator lint_on ASCRANGE // verilator lint_on ASCRANGE
@ -106,6 +107,8 @@ extern "C" int mon_check();
real1 = 1.0; real1 = 1.0;
str1 = "hello"; str1 = "hello";
rev = 12'habc;
`ifdef VERILATOR `ifdef VERILATOR
status = $c32("mon_check()"); status = $c32("mon_check()");
`endif `endif

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@ -37,6 +37,7 @@ extern "C" int mon_check();
// verilator lint_off ASCRANGE // verilator lint_off ASCRANGE
reg [0:61] quads[2:3]; reg [0:61] quads[2:3];
reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */;
// verilator lint_on ASCRANGE // verilator lint_on ASCRANGE
reg [31:0] count; reg [31:0] count;
@ -86,6 +87,8 @@ extern "C" int mon_check();
real1 = 1.0; real1 = 1.0;
str1 = "hello"; str1 = "hello";
rev = 12'habc;
`ifdef VERILATOR `ifdef VERILATOR
status = $c32("mon_check()"); status = $c32("mon_check()");
`endif `endif

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@ -135,6 +135,7 @@ static vpiHandle uvm_hdl_handle_by_name_partsel(char *path, int *is_partsel_ptr,
{ {
vpiHandle rh; vpiHandle rh;
s_vpi_value value; s_vpi_value value;
int req_width_m1;
int decl_ranged = 0; int decl_ranged = 0;
int decl_lo; int decl_lo;
int decl_hi; int decl_hi;
@ -162,12 +163,13 @@ static vpiHandle uvm_hdl_handle_by_name_partsel(char *path, int *is_partsel_ptr,
} }
// vpi_printf((PLI_BYTE8 *)"%s:%d: req %d:%d decl %d:%d for '%s'\n", // vpi_printf((PLI_BYTE8 *)"%s:%d: req %d:%d decl %d:%d for '%s'\n",
// __FILE__, __LINE__, *hi_ptr, *lo_ptr, decl_left, decl_right, path); // __FILE__, __LINE__, *hi_ptr, *lo_ptr, decl_left, decl_right, path);
decl_lo = (decl_left < decl_right) ? decl_left : decl_right; decl_lo = (decl_left > decl_right) ? decl_right : decl_left;
decl_hi = (decl_left > decl_right) ? decl_left : decl_right; decl_hi = (decl_left > decl_right) ? decl_left : decl_right;
if (*lo_ptr < decl_lo) return 0; if (*lo_ptr < decl_lo) return 0;
if (*hi_ptr > decl_hi) return 0; if (*hi_ptr > decl_hi) return 0;
*lo_ptr -= decl_lo; req_width_m1 = *hi_ptr - *lo_ptr;
*hi_ptr -= decl_lo; *lo_ptr = (decl_left > decl_right) ? (*lo_ptr - decl_lo) : (decl_right - *hi_ptr);
*hi_ptr = *lo_ptr + req_width_m1;
} }
return r; return r;
} }

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@ -135,6 +135,7 @@ static vpiHandle uvm_hdl_handle_by_name_partsel(char *path, int *is_partsel_ptr,
{ {
vpiHandle rh; vpiHandle rh;
s_vpi_value value; s_vpi_value value;
int req_width_m1;
int decl_ranged = 0; int decl_ranged = 0;
int decl_lo; int decl_lo;
int decl_hi; int decl_hi;
@ -162,12 +163,13 @@ static vpiHandle uvm_hdl_handle_by_name_partsel(char *path, int *is_partsel_ptr,
} }
// vpi_printf((PLI_BYTE8 *)"%s:%d: req %d:%d decl %d:%d for '%s'\n", // vpi_printf((PLI_BYTE8 *)"%s:%d: req %d:%d decl %d:%d for '%s'\n",
// __FILE__, __LINE__, *hi_ptr, *lo_ptr, decl_left, decl_right, path); // __FILE__, __LINE__, *hi_ptr, *lo_ptr, decl_left, decl_right, path);
decl_lo = (decl_left < decl_right) ? decl_left : decl_right; decl_lo = (decl_left > decl_right) ? decl_right : decl_left;
decl_hi = (decl_left > decl_right) ? decl_left : decl_right; decl_hi = (decl_left > decl_right) ? decl_left : decl_right;
if (*lo_ptr < decl_lo) return 0; if (*lo_ptr < decl_lo) return 0;
if (*hi_ptr > decl_hi) return 0; if (*hi_ptr > decl_hi) return 0;
*lo_ptr -= decl_lo; req_width_m1 = *hi_ptr - *lo_ptr;
*hi_ptr -= decl_lo; *lo_ptr = (decl_left > decl_right) ? (*lo_ptr - decl_lo) : (decl_right - *hi_ptr);
*hi_ptr = *lo_ptr + req_width_m1;
} }
return r; return r;
} }