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Tests: Improve specparam verilog.y coverage

This commit is contained in:
Wilson Snyder 2023-07-05 14:11:55 -04:00
parent dcbc0ccfdc
commit 6f7bc38088
1 changed files with 6 additions and 1 deletions
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7
test_regress/t/t_gate_basic.v
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@ -40,12 +40,17 @@ module t (/*AUTOARG*/
buf BARRAY [BITS-1:0] (ba, a); buf BARRAY [BITS-1:0] (ba, a);
`ifdef verilator `ifdef verilator
specparam RAW_SP = 1;
specify
endspecify
specify specify
specparam CDS_LIBNAME = "foobar"; specparam CDS_LIBNAME = "foobar";
(nt0 *> nt0) = (0, 0); (nt0 *> nt0) = (0, 0);
endspecify endspecify
specify specify
// delay parameters // delay parameters
specparam specparam
a$A1$Y = 1.0, a$A1$Y = 1.0,