New test for bug882.

test_regress/t/t_math_signed6.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_math_signed6.v

@@ -0,0 +1,33 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Iztok Jeras.
+
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
+
+module t (/*AUTOARG*/);
+
+   // signed source
+   logic   signed  [8-1:0] src;
+
+   // destination structure
+   struct packed {
+     logic   signed [16-1:0] s;
+     logic unsigned [16-1:0] u;
+   } dst;
+
+   initial begin
+      // verilator lint_off WIDTH
+      src = 8'sh05;
+      dst = '{s: src, u: src};
+      `checkh (dst.u, 16'h0005);
+
+      src = 8'shf5;
+      dst = '{s: src, u: src};
+      `checkh (dst.u, 16'hfff5);
+      // verilator lint_on WIDTH
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule