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Fix implicit one bit parameter selection, bug603.

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This commit is contained in:
Wilson Snyder
2013-01-16 20:58:48 -05:00
parent f0a4bd28b6
commit 6d1b42bedb
9 changed files with 94 additions and 7 deletions
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src/V3Width.cpp
+11 -1
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@@ -840,7 +840,17 @@ private:
width = 32;
}
// Can't just inherit valuep()->dtypep() as mwidth might not equal width
nodep->dtypeChgWidthSigned(width, nodep->valuep()->widthMin(),issigned);
if (width==1) {
// one bit parameter is same as "parameter [0] foo", not "parameter logic foo"
// as you can extract "foo[0]" from a parameter but not a wire
nodep->dtypeChgWidthSigned(width, nodep->valuep()->widthMin(),issigned);
nodep->dtypep(nodep->findLogicRangeDType
(VNumRange(0,0,false),
nodep->valuep()->widthMin(),
issigned?AstNumeric::SIGNED : AstNumeric::UNSIGNED));
} else {
nodep->dtypeChgWidthSigned(width, nodep->valuep()->widthMin(),issigned);
}
didchk = true;
nodep->valuep()->iterateAndNext(*this,WidthVP(width,nodep->widthMin(),FINAL).p());
}