luke/verilator
1
0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-10-06 18:13:50 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fix implicit one bit parameter selection, bug603.

Browse Source
This commit is contained in:
Wilson Snyder
2013-01-16 20:58:48 -05:00
parent f0a4bd28b6
commit 6d1b42bedb
9 changed files with 94 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/V3AstNodes.cpp
+9
View File
@@ -557,6 +557,15 @@ AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, AstBasicDTypeKwd kw
return newp;
}
AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, AstBasicDTypeKwd kwd,
VNumRange range, int widthMin, AstNumeric numeric) {
AstBasicDType* new1p = new AstBasicDType(fl, kwd, numeric, range, widthMin);
AstBasicDType* newp = findInsertSameDType(new1p);
if (newp != new1p) new1p->deleteTree();
else addTypesp(newp);
return newp;
}
AstBasicDType* AstTypeTable::findInsertSameDType(AstBasicDType* nodep) {
VBasicTypeKey key (nodep->width(), nodep->widthMin(), nodep->numeric(),
nodep->keyword(), nodep->nrange());